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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-13706-1E
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90550A Series
MB90552A/553A/T552A/T553A/F553A/P553A
s DESCRIPTION
The MB90550A series is a line of general-purpose, high-performance, 16-bit microcontrollers designed for applications which require high-speed real-time processing, such as industrial machines, OA equipment, and process control systems. While inheriting the AT architecture of the F2MC*-8 family, the instruction set for the MB90550A series incorporates additional instructions for high-level languages, supports extended addressing modes, and contains enhanced multiplication and division instructions as well as a substantial collection of improved bit manipulation instructions. In addition, the MB90550A has an on-chip 32-bit accumulator which enables processing of long-word data. *: F2MC stands for FUJITSU Flexible Microcontroller.
s FEATURES
* Minimum instruction execution time : 62.5 ns (at oscillation of 4 MHz,xfour times the PLL clock) * Maximum memory space 16 Mbytes * Instruction set optimized for controller applications Supported data types : Bit, byte, word, and long word Typical addressing mode : 23 types Enhanced precision calculation realized by the 32-bit accumulator Enhanced signed multiplication/division instruction and RETI instruction functions
(Continued)
s PACKAGES
100-pin plastic QFP 100-pin plastic LQFP
(FPT-100P-M06)
(FPT-100P-M05)
MB90550A Series
(Continued)
* Instruction set designed for high level language (C) and multi-task operations Adoption of system stack pointer Symmetrical instruction set and barrel shift instructions * Address match detection function integrated (for two address pointers) * Faster execution speed : 4-byte queue * Powerful interrupt functions (Eight priority levels programmable) External interrupt inputs : 8 channels * Data transfer functions (Intelligent I/O service) : Up to 16 channels DTP request inputs : 8 channels * Embedded ROM size (EPROM, Flash : 128 Kbytes) Mask ROM : 64 Kbytes/128 Kbytes * Embedded RAM size (EPROM, Flash : 4 Kbytes) Mask ROM : 2 Kbytes/4 Kbytes * General-purpose ports :Up to 83 channels (Input pull-up resistor settable for : 16 channels Open drain settable for : 8 channels I/O open drains : 6 channels) * A/D converter (RC successive approximation type): 8 channels (Resolution: 8 or 10 bits selectable; Conversion time of 26.3 s minimum) * UART : 1 channel * Extended I/O serial interface : 2 channels * I2C interface : 2 channels (Two channels, including one switchable between terminal input and output) * 16-bit reload timer : 2 channels * 8/16-bit PPG timer : 3 channels (8 bits x 2 channels; 16 bits x 1 channel: Mode switching function provided) * 16-bit I/O timer (Input capture x 4 channels, output compare x 4 channels, free run timer x1 channel * Clock monitor function integrated (Delivering the oscillation clock divided by 21 to 28) * Timebase timer/watchdog timer : 18 bit * Low power consumption modes (sleep, stop, hardware standby, and CPU intermittent operation modes) * Package : QFP-100, LQFP-100 * CMOS technology
2
MB90550A Series
s PRODUCT LINEUP
Part number MB90552A Item Classification ROM size RAM size Mask ROM products Flash ROM products 128 Kbytes 4 Kbytes OTP Evaluation product None 6 Kbytes MB90553A MB90F553A MB90P553A MB90V550A
Mass Product 64 Kbytes 2 Kbytes
CPU functions
The number of instructions: 340 Instruction bit length: 8 bits, 16 bits Instruction length: 1 byte to 7 bytes Data bit length: 1 bit, 8 bits, 16 bits Minimum execution time: 62.5 ns (at machine clock of 16 MHz) Interrupt processing time: 1.5 ms (at machine clock of 16 MHz, minimum value) General-purpose I/O ports (CMOS output): 53 General-purpose I/O ports (with pull-up resistor): 16 General-purpose I/O ports (N-channel open-drain output): 6 General-purpose I/O ports (N-channel open-drain function selectable): 8 Total: 83 Clock synchronized transmission (62.5 kbps to 2 Mbps) Clock asynchronized transmission (62500 bps to 9615 bps) Transmission can be performed by bi-directional serial transmission or by master/slave connection. Resolution: 8/10-bit Number of inputs: 8 One-shot conversion mode (converts selected channel only once) Scan conversion mode (converts two or more successive channels and can program up to 8 channels.) Continuous conversion mode (converts selected channel continuously) Stop conversion mode (converts selected channel and stop operation repeatedly) Number of channels: 1 (or 8-bit x 2 channels) PPG operation of 8-bit or 16-bit A pulse wave of given intervals and given duty ratios can be output. Pulse interval: 62.5 ns to 1 ms (at oscillation of 4 MHz, machine clock of 16 MHz) Number of channel: 1 Overflow interrupts Number of channels: 4 Pin input factor: A match signal of compare register Number of channels: 4 Rewriting a register value upon a pin input (rising, falling, or both edges)
Ports
UART0 (SCI)
8/10-bit A/D converter
8/16-bit PPG timer
16-bit free run timer 16-bit I/O timer Output compare (OCU) Input capture (ICU)
(Continued)
3
MB90550A Series
(Continued)
Part number MB90552A Item DTP/external interrupt circuit Extended I/O serial interface I2C interface Timebase timer Number of inputs: 8 Started by a rising edge, a falling edge, an "H" level input, or an "L" level input. External interrupt circuit or extended intelligent I/O service (EI2OS) can be used. Clock synchronized transmission (3125 bps to 1 Mbps) LSB first/MSB first Serial I/O port for supporting Inter IC BUS 18-bit counter Interrupt interval: 1.024 ms, 4.096 ms, 16.384 ms, 131.072 ms (at oscillation of 4 MHz) Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms (at oscillation of 4 MHz, minimum value) CMOS 4.5 V to 5.5 V MB90553A MB90F553A MB90P553A MB90V550A
Watchdog timer Process Power supply voltage for operation*
*:Varies with conditions such as the operating frequency. (See section "s ELECTRICAL CHARACTERISTICS") Assurance for the MB90V550A is given only for operation with a tool at a power voltage of 4.5 V to 5.5 V, an operating temperature of 0 to +25C, and an operating frequency of 1 MHz to 16 MHz.
s PACKAGE AND CORRESPONDING PRODUCTS
Package FPT-100P-M05 FPT-100P-M06 : Available x : Not available MB90552A MB90553A MB90F553A MB90P553A x
Note:For more information about each package, see section "s PACKAGE DIMENSIONS"
s DIFFERENCES AMONG PRODUCTS
Memory Size In evaluation with an evaluation product, note the difference between the evaluation product and the product actually used. The following items must be taken into consideration. * The MB90V550A does not have an internal ROM, however, operations equivalent to chips with an internal ROM can be evaluated by using a dedicated development tool, enabling selection of ROM size by settings of the development tool. * In the MB90V550, images from FF4000H to FFFFFFH are mapped to bank 00, and FE0000H to FF3FFFH to mapped to bank FE and FF only. (This setting can be changed by configuring the deveolpment tool.) * In the MB90F553A/553A/552A, images from FF4000H to FFFFFFH are mapped to bank 00, and FF0000H to FF3FFFH to bank FF only.
4
MB90550A Series
s PIN ASSIGNMENT
* FPT-100P-M06 (Top view)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
P17/AD15 P16/AD14 P15/AD13 P14/AD12 P13/AD11 P12/AD10 P11/AD09 P10/AD08 P07/AD07 P06/AD06 P05/AD05 P04/AD04 P03/AD03 P02/AD02 P01/AD01 P00/AD00 VCC X1 X0 VSS
P20/A16 P21/A17 P22/A18 P23/A19 P24/A20 P25/A21 P26/A22 P27/A23 P30/ALE P31/RD VSS P32/WRL P33/WRH P34/HRQ P35/HAK P36/RDY P37/CLK P40/SCK P41/SOT P42/SIN P43/SCK1 P44/SOT1 VCC P45/SIN1 P46/ADTG P47/SCK0 C P50/SDA0/SOT0 P51/SCL0/SIN0 P52/SDA1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
PA4/CKOT PA3 PA2 RST PA1/OUT3 PA0/OUT2 P97/PPG5 P96/PPG4 P95/PPG3 P94/PPG2 P93/PPG1 P92/PPG0 P91/OUT1 P92/OUT0 P87/IN3 P86/IN2 P85/IN1 P84/IN0 P83/TOT1 P82/TOT0 P81/TIN1 P80/TIN0 P77/IRQ7 P76/IRQ6 P75/IRQ5 P74/IRQ4 P73/IRQ3 P72/IRQ2 HST MD2
P53/SCL1 P54/SDA2 P55/SCL2 AVCC AVRH AVRL AVSS P60/AN0 P61/AN1 P62/AN2 P63/AN3 VSS P64/AN4 P65/AN5 P66/AN6 P67/AN7 P70/IRQ0 P71/IRQ1 MD0 MD1
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
(FPT-100P-M06)
5
MB90550A Series
* FPT-100P-M05 (Top view)
P22/A18 P23/A19 P24/A20 P25/A21 P26/A22 P27/A23 P30/ALE P31/RD VSS P32/WRL P33/WRH P34/HRQ P35/HAK P36/RDY P37/CLK P40/SCK P41/SOT P42/SIN P43/SCK1 P44/SOT1 VCC P45/SIN1 P46/ADTG P47/SCK0 C
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
100 P21/A17 99 P20/A16 98 P17/AD15 97 P16/AD14 96 P15/AD13 95 P14/AD12 94 P13/AD11 93 P12/AD10 92 P11/AD09 91 P10/AD08 90 P07/AD07 89 P06/AD06 88 P05/AD05 87 P04/AD04 86 P03/AD03 85 P02/AD02 84 P01/AD01 83 P00/AD00 82 VCC 81 X1 80 X0 79 VSS 78 PA4/CKOT 77 PA3 76 PA2
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
RST PA1/OUT3 PA0/OUT2 P97/PPG5 P96/PPG4 P95/PPG3 P94/PPG2 P93/PPG1 P92/PPG0 P91/OUT1 P90/OUT0 P87/IN3 P86/IN2 P85/IN1 P84/IN0 P83/TOT1 P82/TOT0 P81/TIN1 P80/TIN0 P77/IRQ7 P76/IRQ6 P75/IRQ5 P74/IRQ4 P73/IRQ3 P72/IRQ2
6
P50/SDA0/SOT0 P51/SCL0/SIN0 P52/SDA1 P53/SCL1 P54/SDA2 P55/SCL2 AVCC AVRH AVRL AVSS P60/AN0 P61/AN1 P62/AN2 P63/AN3 VSS P64/AN4 P65/AN5 P66/AN6 P67/AN7 P70/IRQ0 P71/IRQ1 MD0 MD1 MD2 HST
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
(FPT-100P-M05)
MB90550A Series
s PIN DESCRIPTION
Pin no. QFP 82 83 77 52 LQFP 80 81 75 50 Pin name X0 X1 RST HST Circuit type A A B C Oscillation pin Oscillation pin Reset input pin Hardware standby input pin General-purpose I/O port. A pull-up resistor can be added (RD07 to RD00 = 1) by using the pull-up resistor setting register (RDR0). D07 to D00 = 1: Disabled when the port is set for output. Serve as lower data I/O/lower address output (AD00 to AD07) pins in the external bus mode. General-purpose I/O port. A pull-up resistor can be added (RD17 to RD10 = 1) by using the pull-up resistor setting register (RDR1). D17 to D10 = 1: Disabled when the port is set for output. Serve as upper data I/O/middle address output (AD08 to AD15) pins in the 16-bit bus-width, external bus mode. General-purpose I/O port. This function is enabled either in single-chip mode or with the xternal address output control register set to "Port". External address bus A16 to A23 output pins. This function is enabled in an external-bus enabled mode with the external address output register set to "Address". General-purpose I/O port. This function is enabled in single-chip mode. Address latch enable output pin. This function is enabled in an external-bus enabled mode. General-purpose I/O port. This function is enabled in single-chip mode. Read strobe output pin for the data bus. This function is enabled in an external-bus enabled mode. General-purpose I/O port. This function is enabled in single-chip mode. Write strobe output pin for the lower eight bits of the data bus. This function is enabled in an external-bus enabled mode. General-purpose I/O port. This function is enabled in single-chip mode. Write strobe output pin for the upper eight bits of the data bus. This function is enabled in an external-bus enabled mode. Function
P00 to P07 85 to 92 83 to 90 AD00 to AD07
D (CMOS)
93 to 100
P10 to P17 91 to 98 AD08 to AD15 P20 to P27
D (CMOS)
1 to 8
99,100, 1 to 6 A16 to A23
E (CMOS)
P30 9 7 ALE P31 10 8 RD P32 12 10 WRL P33 13 11 WRH
E (CMOS)
E (CMOS)
E (CMOS)
E (CMOS)
(Continued)
7
MB90550A Series
Pin no. QFP LQFP
Pin name P34
Circuit type
Function General-purpose I/O port. This function is enabled in single-chip mode Hold request input pin. This function is enabled in an external-bus enabled mode. General-purpose I/O port. This function is enabled in single-chip mode. Hold acknowledge output pin. This function is enabled in an external-bus enabled mode. General-purpose I/O port. This function is enabled in single-chip mode. Ready signal input pin. This function is enabled in an external-bus enabled mode. General-purpose I/O port. This function is enabled in single-chip mode. CLK output pin. This function is enabled in an external-bus enabled mode. General-purpose I/O port. Serves as an open-drain output port (OD40 = 1) depending on the setting of the open-drain control setting register (ODR4). (D40 = 0: Disabled when the port is set for input.) UART serial clock I/O pin. This function is enabled with the UART clock output enabled. General-purpose I/O port. Serves as an open-drain output port (OD41 = 1) depending on the setting of the open-drain control setting register (ODR4). (D41 = 0: Disabled when the port is set for input.) UART serial data output pin. This function is enabled with the UART serial data output enabled. General-purpose I/O port. Serves as an open-drain output port (OD42 = 1) depending on the setting of the open-drain control setting register (ODR4). (D42 = 0: Disabled when the port is set for input.) UART serial data input pin. Since this input is used as required while the UART is operating for input, the output by any other function must be off unless used intentionally. General-purpose I/O port. Serves as an open-drain output port (OD43 = 1) depending on the setting of the open-drain control setting register (ODR4). (D43 = 0: Disabled when the port is set for input.) Extended I/O serial clock I/O pin. This function is enabled with the extended I/O serial clock output enabled.
14
12 HRQ P35
E (CMOS)
15
13 HAK P36
E (CMOS)
16
14 RDY P37
E (CMOS)
17
15 CLK
E (CMOS)
P40 18 16 SCK
F (CMOS/H)
P41 19 17 SOT
F (CMOS/H)
P42 20 18 SIN F (CMOS/H)
P43 21 19 SCK1
F (CMOS/H)
(Continued)
8
MB90550A Series
Pin no. QFP LQFP
Pin name
Circuit type
Function General-purpose I/O port. Serves as an open-drain output port (OD44 = 1) depending on the setting of the open-drain control setting register (ODR4). (D44 = 0: Disabled when the port is set for input.) Extended I/O serial data output pin. This function is enabled with the extended I/O serial data output enabled. General-purpose I/O port. Serves as an open-drain output port (OD45 = 1) depending on the setting of the open-drain control setting register (ODR4). (D45 = 0: Disabled when the port is set for input.) Extended I/O serial data input pin. Since this input is used as required while the extended I/O serial interface is operating for input, the output by any other function must be off unless used intentionally. General-purpose I/O port. Serves as an open-drain output port (OD46 = 1) depending on the setting of the open-drain control setting register (ODR4). (D46 = 0: Disabled when the port is set for input.) A/D converter external trigger input pin. Since this input is used as required while the A/D converter is operating for input, the output by any other function must be off unless used intentionally. General-purpose I/O port. Serves as an open-drain output port (OD47 = 1) depending on the setting of the open-drain control setting register (ODR4). D47 = 0: Disabled when the port is set for input. Extended I/O serial clock I/O pin. This function is enabled with the extended I/O serial clock output enabled.
P44 22 20 SOT1 F (CMOS/H)
P45 24 22 SIN1 F (CMOS/H)
P46 25 23 ADTG F (CMOS/H)
P47 26 24 SCK0 27 25 C P50
F (CMOS/H)
--
Capacitance pin for regulating the power supply. Connect an external ceramic capacitor of about 0.1 F. N-channel open-drain I/O port. I2C interface data I/O pin. This function is enabled with the I2C interface enabled for operation. While the I2C interface is operating, place the port output in the Hi-Z state (PDR = 1). Extended I/O serial data output pin. This function is enabled with the extended I/O serial data output enabled.
SDA0 28 26
G (NchOD/H)
SOT0
(Continued)
9
MB90550A Series
Pin no. QFP LQFP
Pin name P51
Circuit type
Function N-channel open-drain I/O port. I2C interface clock I/O pin. This function is enabled with the I2C interface enabled for operation. While the I2C interface is operating, place the port output in the Hi-Z state (PDR = 1). Extended I/O serial data input pin. Since this input is used as required while the extended I/O serial interface is operating for input, the output by any other function must be off unless used intentionally. N-channel open-drain I/O port. I2C interface data I/O pins. This function is enabled with the I2C interface enabled for operation. While the I2C interface is operating, place the port output in the Hi-Z state (PDR = 1). N-channel open-drain I/O port. I2C interface clock I/O pins. This function is enabled with the I2C interface enabled for operation. While the I2C interface is operating, place the port output in the Hi-Z state (PDR = 1). General-purpose I/O port. A/D converter analog input pin. This function is enabled with the analog input enabled. General-purpose I/O port. External interrupt request input pins. Since this input is used as required while external interrupts remain enabled, the output by any other function must be off unless used intentionally. General-purpose I/O port. Reload timer event input pins. Since this input is used as required while the reload timer is operating for input, the output by any other function must be off unless used intentionally. General-purpose I/O port. Reload timer output pins. General-purpose I/O port. Input capture trigger input pin. Since this input is used as required while the input capture unit is operating for input, the output by any other function must be off unless used intentionally. General-purpose I/O port. Output compare event output pins.
SCL0 29 27 G (NchOD/H) SIN0
P52,P54 30,32 28,30 SDA1,SDA2 P53,P55 31,33 29,31 SCL1,SCL2 P60 to P67 AN0 to AN7 P70 to P77 47,48, 45,46, 53 to 58 51 to 56 IRQ0 to IRQ7 P80,P81 59,60 57,58 TIN0,TIN1 P82,P83 TOT0,TOT1 P84 to P87 63 to 66 61 to 64 J (CMOS/H) J (CMOS/H) I (CMOS/H) G (NchOD/H) G (NchOD/H)
38 to 41, 36 to 39, 43 to 46 41 to 44
H (CMOS/H)
61,62
59,60
J (CMOS/H)
IN0 to IN3
67,68
65,66
P90,P91 OUT0,OUT1
J (CMOS/H)
(Continued)
10
MB90550A Series
(Continued) Pin no.
QFP LQFP
Pin name P92 to P97
Circuit type J (CMOS/H) J (CMOS/H) J (CMOS/H) J (CMOS/H) C General-purpose I/O port.
Function
69 to 74 67 to 72
PPG0 to PPG5 PA0,PA1 OUT2,OUT3 PA2,PA3 PA4 CKOT AVCC AVRH AVRL AVSS MD0,MD1
PPG output pins. This function is enabled with the PPG output enabled. General-purpose I/O port. Output compare event output pins. General-purpose I/O port. General-purpose I/O port. Serves as the CKOT output while the CKOT is operating. A/D converter power-supply pin. This is a general purpose I/O port. A/D converter external reference voltage source pin. A/D converter power-supply pin. Operation mode setting input pins. Connect these pins directly to Vcc or Vss. Operation mode setting input pin. Connect this pin directly to Vcc or Vss. (MB90552A/553A/ V550A) Operation mode setting input pin. Connect this pin directly to Vcc or Vss. (MB90P553A/F553A) Power (5 V) input pin. Power (0 V) input pin.
75,76 78,79 80 34 35 36 37
73,74 76,77 78 32 33 34 35
49 to 50 47 to 48
K 51 49 MD2 C 23,84 11,42, 81 21,82 9,40, 79 VCC VSS
11
MB90550A Series
s I/O CIRCUIT TYPE
Type Circuit
Clock input
X1
Remarks * 3 MHz to 32 MHz * Oscillator recovery resistor approx. 1M
A
X0
HARD,SOFT STANDBY CONTROL
* CMOS level hysteresis input * Pull-up resistor provided Resistor : About 50 k B
* CMOS level hysteresis input C * * * * CMOS level output CMOS level input Standby control provided Input pull-up resistor control provided Resistor: About 50 k
Pull-up resistor control
Digital output
Digital output
D
Digital input
HARD,SOFT STANDBY CONTROL
(Continued)
12
MB90550A Series
Type
Circuit
Remarks * CMOS level output * CMOS level input * Standby control provided
Digital output Digital output
E
Digital input
HARD,SOFT STANDBY CONTROL
Open- drain control signal Digital input
* CMOS level output * CMOS level hysteresis input * Open-drain control provided
F
Digital input
HARD,SOFT STANDBY CONTROL
Digital output
G
Digital input
HARD,SOFT STANDBY CONTROL
* N-channel open-drain output * CMOS level hysteresis input * Standby control provided Note: Unlike normal CMOS I/O pins, this pin is not provided with any P-channel transistor. Therefore the pin does not allow a current to flow to the Vcc side even when applied with a voltage from an external device with the IC's power supply left off.
Digital output
* * * *
CMOS level output CMOS level hysteresis input Standby control provided Analog input
Digital output
H
Analog input Digital input
HARD,SOFT STANDBY CONTROL
A/D DISABLE
(Continued)
13
MB90550A Series
(Continued) Type
Circuit
Remarks * CMOS level output * CMOS level hysteresis input * Standby control provided
Digital output
Digital output
I
Digital input
HARD STANDBY CONTROL
Digital output
* CMOS level output * CMOS level hysteresis input * Standby control provided
Digital output
J
Digital input
HARD,SOFT STANDBY CONTROL
* CMOS level hysteresis input * Pull-up resistor provided Resistor : About 50k K
14
MB90550A Series
s HANDLING DEVICES
1. Preventing Latchup
CMOS ICs may cause latchup in the following situations: * When a voltage higher than Vcc or lower than Vss is applied to input or output pins. * When a voltage exceeding the rating is applied between Vcc and Vss. * When AVcc power is supplied prior to the Vcc voltage. If latchup occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the device. Use meticulous care not to let it occur. For the same reason, also be careful not to let the analog power-supply voltage exceed the digital power-supply voltage.
2. Connection of Unused Pins
Leaving unused pins open may result in abnormal operations. Clamp the pin level by connecting it to a pull-up or a pull-down 1k or more resistor.
3. Notes on Using External Clock
In using the external clock, drive X0 pin only and leave X1 pin unconnected. * Using external clock MB90550A series
X0
Open
X1
4. Power Supply Pins (VCC/VSS)
In products with multiple VCC or VSS pins, the pins of a same potential are internally connected in the device to avoid abnormal operations including latch-up. However, connect the pins external power and ground lines to lower the electro-magnetic emission level and abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total current rating. Make sure to connect VCC and VSS pins via lowest impedance to power lines. It is recommended to provide a bypass capacitor of around 0.1 F between VCC and VSS pin near the device. * Using power supply pins
VCC VSS
VCC VSS VCC MB90550A series
VSS
VCC VSS
VSS
VCC
15
MB90550A Series
5. Crystal Oscillator Circuit
Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other circuits. It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with an grand area for stabilizing the operation.
6. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
Make sure to turn on the A/D converter power supply, D/A converter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to AN7) after turning-on the digital power supply (VCC). Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure that the voltage not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simultaneously is acceptable).
7. Connection of Unused Pins of A/D Converter
Connect unused pin of A/D converter to AVCC = VCC, AVSS = AVRH = AVRL = VSS.
8. N.C. Pin
The N.C. (internally connected) pin must be opened for use.
9. Notes on Energization
To prevent the internal regulator circuit rom malfunctioning,set the voltage rise time during energization at 50 or more s.
10. Initialization
In the device, there are internal registers which is initialized only by a power-on reset. To initialize these registers turning on the power again.
11. Return from standby state
If the power-supply voltage goes below the standby RAM holding voltage in the standby state, the device may fail to return from the standby state. In this case, reset the device via the external reset pin to return to the normal state.
12. Precautions for Use of 'DIV A, Ri,' and 'DIVW A, Ri' Instructions
The signed multiplication-division instructions 'DIV A, Ri,' and 'DIVW A, RWi' should be used when the corresponding bank registers (DTB, ADB, USB, SSB) are set to value '00h.' If the corresponding bank registers (DTB, ADB, USB, SSB) are set to a value other than '00h,' then the remainder obtained after the execution of the instruction will not be placed in the instruction operand register.
16
MB90550A Series
s BLOCK DIAGRAM
X0, X1 RST HST RAM ROM P00 to P07/ AD00 to AD07 P10 to P17/ AD08 to AD15 P20 to P27/ A16 to A23 P30/ALE P31/RD P32/WRL P33/WRH P34/HRQ P35/HAK P36/RDY P37/CLK 4
Clock control circuit*
CPU
Core of F2MC-16LX family
Interrupt controller
Port A
F F M C 16 L X B U S
Clock monitor function
Port 0 Port 1 Port 2 Port 3
CKOT/PA4 PA2, A3 OUT2, OUT3/ PA0, A1
Port 9
PPG5/P97 PPG4/P96
8/16 PPG x 3c h
PPG3/P95 PPG2/P94 PPG1/P93
I/O timer
16-bit output compare unit x 4 channels 16-bit input capture unit x 4 channels 16-bit free-run timer
PPG0/P92 OUT0, OUT1/ P90, P91 IN0 to IN3/ P84 to P87
Port 4
Communication prescaler
16-bit reload timer x 2 channels
TOT0, TOT1/ P82, P83 TIN0, TIN1/ P80, P81
P40/SCK P41/SOT P42/SIN P43/SCK1 P44/SOT1 P45/SIN1 P46/ADTG AVCC P47/SCK0 P50/SDA0/SOT0 P51/SCL0/SIN0 P52/SDA1 P53/SCL1 P54/SDA2 P55/SCL2 UART
Port 8 Port 7
Extended I/O serial interface 1
External interrupt
IRQ0 to IRQ7/ P70 to P77
Extended I/O serial interface 0
A/D converter (8/10 bits)
AVRH, AVRL AVSS AN0 to AN7/ P60 to P67
I2C interface 0
Port 6 *: Specifications of evaluation model
I2C interface 1 Port 5
(MB90V550A)
Contains no internal ROM. Contains 6 KB of internal RAM. Contains the same internal resources as the other products in the MB90550A series.
17
MB90550A Series
Note: The clock control circuit contains a watchdog timer, time-base timer, and a low power consumption control circuit. P00 to P07 (8 pins): Input pull-up resistor setting register provided P10 to P17 (8 pins): Input pull-up resistor setting register provided P40 to P47 (8 pins): Open-drain control setting register provided P50 to P55 (6 pins): N-channel open drain Ports 0, 1, 2, 3, 4, 6, 7, 8, 9, and A are CMOS level input/output ports.
18
MB90550A Series
s MEMORY MAP
The ROM data of bank FF is reflected in the upper address of bank 00, realizing effective use of the C compiler small model. The lower 16-bit of bank FF and the lower 16-bit of bank 00 is assigned to the same address, enabling reference of the table on the ROM without stating "far". For example, if an attempt has been made to access 00C000H, the contents of the ROM at FFC000H are accessed actually. Since the ROM area of the FF bank exceeds 48 Kbytes, the whole area cannot be reflected in the image for the 00 bank. The ROM data at FF4000H to FFFFFFH looks, therefore, as if it were the image for 004000H to 00FFFFH. Thus, it is recommended that the ROM data table be stored in the area of FF4000H to FFFFFFH.
Internal ROM Single chip mode
A mirror function is supported external bus mode A mirror function is supported
External ROM
external bus mode
FFFFFFH ROM area Address#1 ROM area
FF0000H 010000H
Address#2
ROM area (image of bank FF)
ROM area (image of bank FF)
004000H 002000H Address#3
RAM Registor RAM Registor RAM Registor
: Internal access memory : External access memory : Inhibited area
000100H 0000C0H 0000D0H
Peripheral
Peripheral
Peripheral
Parts No.
MB90552A MB90553A MB90F553A MB90P553A MB90V550A
Address#1
FF0000H FE0000H FE0000H FE0000H (FE0000H)
Address#2
004000H 004000H 004000H 004000H 004000H
Address#3
000900H 001100H 001100H 001100H 001900H
19
MB90550A Series
s F2MC-16LX CPU PROGRAMMING MODEL
* Dedicated registers
: Accumlator (A) Dual 16-bit register used for storing results of calculation etc. The two 16-bit registers can be combined to be used as a 32-bit register. : User stack pointer (USP) The 16-bit pointer indicating a user stack address. : System stack pointer (SSP) The 16-bit pointer indicating the status of the system stack address. : Processor status (PS) The 16-bit register indicating the system status. : Program counter (PC) The 16-bit register indicating storing location of the current instruction code. : Direct page register (DPR) The 8-bit register indicating bit 8 through 15 of the operand address in the short direct addressing mode. : Program bank register (PCB) The 8-bit register indicating the program space. : Data bank register (DTB) The 8-bit register indicating the data space. : User stack bank register (USB) The 8-bit register indicating the user stack space. : System stack bank register (SSB) The 8-bit register indicating the system stack space. : Additional data bank register (ADB) The 8-bit register indicating the additional data space.
AH
AL
USP
SSP
PS
PC
DPR
PCB
DTB
USB
SSB
ADB
8 bit 16 bit 32 bit
20
MB90550A Series
s I/O MAP
Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH to 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H Analog input enable register Serial mode register Serial control register Serial input data register / serial output data register Serial status register
ADER
Register name Port 0 data register Port 1 data register Port 2 data register Port 3 data register Port 4 data register Port 5 data register Port 6 data register Port 7 data register Port 8 data register Port 9 data register Port A data register
Abbreviated register name PDR0 PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 PDR7 PDR8 PDR9 PDRA
Read/write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Resource name Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A
Initial value
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX __111111 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX _ _ _XXXXX
(Disabled) Port 0 direction register Port 1 direction register Port 2 direction register Port 3 direction register Port 4 direction register Port 6 direction register Port 7 direction register Port 8 direction register Port 9 direction register Port A direction register Port 4 output pin register Port 0 resistor setting register Port 1 resistor setting register DDR0 DDR1 DDR2 DDR3 DDR4 DDR6 DDR7 DDR8 DDR9 DDRA ODR4 RDR0 RDR1 R/W R/W R/W R/W R/W (Disabled) R/W R/W R/W R/W R/W R/W R/W R/W (Disabled)
R/W
Port 0 Port 1 Port 2 Port 3 Port 4 Port 6 Port 7 Port 8 Port 9 Port A Port 4 Port 0 Port 1 Port 6, A/D converter
00000000 00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000 ___00000 00000000 00000000 00000000
11111111 00000000 0 0 0 0 0 10 0
SMR SCR SIDR/SODR SSR
R/W R/W R/W R/W UART
XXXXXXXX 00001_00
(Continued)
21
MB90550A Series
Address 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH
Register name Serial mode control status register 0 Serial mode control status register 0 Serial data register 0 Clock frequency-divider control register Serial mode control status register 1 Serial mode control status register 1 Serial data register 1 I C bus status register 0 I C bus control register 0 I2C bus clock select register 0 I2C bus address register 0 I C bus data register 0 I2C bus status register 1 I2C bus control register 1 I C bus clock select register 1
2
Abbreviated register name
Read/write R/W
Resource name
Initial value
____0000
SMCS0 R/W! SDR0 CDCR R/W R/W R/W SMCS1 R/W! SDR1 IBSR0 IBCR0 ICCR0 IADR0 IDAR0 IBSR1 IBCR1 ICCR1 IADR1 IDAR1 ISEL ENIR EIRR ELVR ADCS0 ADCS1 ADCR0 ADCR1 R/W (Disabled) R R/W R/W R/W R/W (Disabled) R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W! R/W
Extended I/O serial interface 0
00000010 XXXXXXXX
Communication prescaler
0___1111 ____0000
Extended I/O serial interface 1
00000010 XXXXXXXX
2 2
00000000 00000000
I2C interface 0
_ _ 0XXXXX _ XXXXXXX XXXXXXXX
2
00000000 00000000
I C bus address register 1 I2C bus data register 1 I2C bus port select register Interrupt/DTP enable register Interrupt/DTP factor register Request level setting register Control status register Data register
2
I2C interface 1
_ _ 0XXXXX _ XXXXXXX XXXXXXXX _______0 00000000
DTP/externalint interrupt
XXXXXXXX 00000000 00000000 00000000
A/D convertor
00000000 XXXXXXXX XXXXXXXX
(Continued)
22
MB90550A Series
Address 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH 50H 51H 52H 53H 54H 55H 56H 57H 58H 59H
Register name Reload register L (ch.0) Reload register H (ch.0) Reload register L (ch.1) Reload register H (ch.1) PPG0 operating mode control register PPG1 operating mode control register PPG0 and 1 output control register Reload register L (ch.2) Reload register H (ch.2) Reload register L (ch.3) Reload register H (ch.3) PPG2 operating mode control register PPG3 operating mode control register PPG2 and 3 output control register Reload register L (ch.4) Reload register H (ch.4) Reload register L (ch.5) Reload register H (ch.5) PPG4 operating mode control register PPG5 operating mode control register PPG4 and 5 output control register
Abbreviated register name PRLL0 PRLH0 PRLL1 PRLH1 PPGC0 PPGC1 PPGE1
Read/write R/W R/W R/W R/W R/W R/W R/W
Resource name
Initial value
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
8/16 bit PPG0/1
0_000__1 0_000001 00000000
(Disabled) PRLL2 PRLH2 PRLL3 PRLH3 PPGC2 PPGC3 PPGE2 R/W R/W R/W R/W R/W R/W R/W 8/16 bit PPG2/3
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0_000__1 0_000001 00000000
(Disabled) PRLL4 PRLH4 PRLL5 PRLH5 PPGC4 PPGC5 PPGE3 R/W R/W R/W R/W R/W R/W R/W 8/16 bit PPG4/5
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0_000__1 0_000001 00000000
(Disabled) Clock output enable register CLKR R/W (Disabled) Clock monitor function
____0000
(Continued)
23
MB90550A Series
Address 5AH 5BH 5CH 5DH 5EH 5FH 60H 61H 62H 63H 64H 65H 66H 67H 68H 69H 6AH 6BH 6CH 6DH 6EH 6FH
Register name Control status register 0 16 bit timer register 0/ 16 bit reload register 0 Control status register 1 16 bit timer register 1/ 16 bit reload register 1 Input capture register, channel-0 lower bits Input capture register, channel-0 upper bits Input capture register, channel-1 lower bits Input capture register, channel-1 upper bits Input capture register, channel-2 lower bits Input capture register, channel-2 upper bits Input capture register, channel-3 lower bits Input capture register, channel-3 upper bits Input capture control status register Input capture control status register Timer data register, lower bits Timer data register, upper bits Timer control status register ROM mirroring function selection register
Abbreviated register name TMCSR0 TMR0/ TMRLR0 TMCSR1 TMR1/ TMRLR1
Read/write R/W
Resource name
Initial value
00000000
16 bit reload timer 0 R/W R/W 16 bit reload timer 1 R/W
____0000 XXXXXXXX XXXXXXXX 00000000 ____0000 XXXXXXXX XXXXXXXX XXXXXXXX
IPCP0
R
XXXXXXXX XXXXXXXX
IPCP1
R
XXXXXXXX
IPCP2
R
16 bit I/O timer Input capture (ch.0 to ch.3)
XXXXXXXX XXXXXXXX XXXXXXXX
IPCP3
R
XXXXXXXX
ICS01 ICS23 TCDT TCCS ROMM
R/W R/W R/W R/W R/W W 16 bit I/O timer free run timer ROM mirroring function
00000000 00000000 00000000 00000000 00000000 _______1
(Continued)
24
MB90550A Series
Address 70H 71H 72H 73H 74H 75H 76H 77H 78H 79H 7AH 7BH 7CH to 9DH 9EH 9FH A0H A1H A2H to A4H A5H A6H A7H
Register name Compare register, channel-0 lower bits Compare register, channel-0 upper bits Compare register, channel-1 lower bits Compare register, channel-1 upper bits Compare register, channel-2 lower bits Compare register, channel-2 upper bits Compare register, channel-3 lower bits Compare register, channel-3 upper bits Compare control status register, channel-0 Compare control status register, channel-1 Compare control status register, channel-2 Compare control status register, channel-3
Abbreviated register name
Read/write
Resource name
Initial value
XXXXXXXX
OCCP0
R/W
XXXXXXXX XXXXXXXX
OCCP1
R/W
XXXXXXXX XXXXXXXX
OCCP2
R/W
16 bit I/O timer output compare (ch.0 to ch.3)
XXXXXXXX XXXXXXXX XXXXXXXX
OCCP3
R/W
OCS0 OCS1 OCS2 OCS3
R/W R/W R/W R/W (Disabled)
0000__00 ___00000 0000__00 ___00000
Program address detection control register Delayed interrupt factor generation/cancellation register Low-power consumption mode control register Clock select register
PACSR DIRR LPMCR CKSCR
R/W R/W R/W! R/W!
Address match detection function Delayed interrupt
00000000 _______0
Low power 00011000 consumption control 11111100 circuit
(Disabled) Automatic ready function select register External address output control register Bus control signal select register ARSR HACR ECSR W W W External bus pin control circuit
0011__00 00000000 0000000_
(Continued)
25
MB90550A Series
Address A8H A9H AAH to ADH AEH AFH B0H B1H B2H B3H B4H B5H B6H B7H B8H B9H BAH BBH BCH BDH BEH BFH C0H to FFH 100H to #H #H to 1FEFH
Register name Watchdog timer control register Timebase timer control register
Abbreviated register name WDTC TBTC
Read/write R/W! R/W!
Resource name Watchdog timer Timebase timer
Initial value
XXXXX 1 1 1 1__00100
(Disabled) Flash control status register FMCS R/W (Disabled) Interrupt control register 00 Interrupt control register 01 Interrupt control register 02 Interrupt control register 03 Interrupt control register 04 Interrupt control register 05 Interrupt control register 06 Interrupt control register 07 Interrupt control register 08 Interrupt control register 09 Interrupt control register 10 Interrupt control register 11 Interrupt control register 12 Interrupt control register 13 Interrupt control register 14 Interrupt control register 15 ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 R/W! R/W! R/W! R/W! R/W! R/W! R/W! R/W! R/W! R/W! R/W! R/W! R/W! R/W! R/W! R/W! Interrupt controller
00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111
Flash interface circuit
00000__0
(External area) (RAM area) (Reserved area)
(Continued)
26
MB90550A Series
(Continued)
Address 1FF0H 1FF1H 1FF2H 1FF3H 1FF4H 1FF5H 1FF6H to 1FFFH Register name Program address detection register 0 Program address detection register 1 Program address detection register 2 Program address detection register 3 Program address detection register 4 Program address detection register 5 PADR1 PADR0 Abbreviated register name Read/write R/W R/W R/W R/W R/W R/W (Reserved area) Resource name Initial value
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Address match detection function
* Initial value representations 0: Initial value of 0 1: Initial value of 1 X: Initial value undefined -: Initial value undefined (none) * Addresses that follow 00FFH are a reserved area. * The boundary #H between the RAM and reserved areas is different depending on each product. Note : For writable bits, the initial value column contains the initial value to which the bit is initialized at a reset. Notice that it is not the value read from the bit. The LPMCR, CKSCR, and WDTC registers may be initialized or not at a reset, depending on the type of the reset. Their initial values in the above list are those to which the registers are initialized, of course. "R/W!" in the access column indicates that the register contains read-only or write-only bits. If a read-modify-write instruction (such as a bit setting instruction) is used to access a register marked "R/ W!" "R/W*", or "W" in the access column, the bit focused on by the instruction is set to the desired value but a malfunction occurs if the other bits contains a write-only bit. Do not use such instructions to access those registers.
27
MB90550A Series
s INTERRUPT FACTORS
INTERRUPT VECTORS, INTERRUPT CONTROL REGISTERS Interrupt vectors EI2OS Interrupt source support Number Address Reset INT9 instruction Exception A/D converter Timebase timer DTP0 (external interrupt 0) DTP4/5 (external interrupt 4/5) DTP1 (external interrupt 1) 8/16-bit PPG timer0 counter borrow DTP2 (external interrupt 2) 8/16-bit PPG timer 1 counter borrow DTP3 (external interrupt 3) 8/16-bit PPG timer 2 counter borrow Extended I/O serial interface 0 8/16-bit PPG timer 3 counter borrow Extended I/O serial interface 1 16-bit free-run timer (I/O timer) overflow 16-bit re-load timer 0 DTP6/7 (external interrupt 6/7) 16-bit re-load timer 1 8/16-bit PPG timer 4/5 counter borrow Input capture (ch.0) include (I/O timer) Input capture (ch.1) include (I/O timer) Input capture (ch.2) include (I/O timer) Input capture (ch.3) include (I/O timer) Output compare (ch.0) match (Output timer) Output compare (ch.1) match (Output timer) Output compare (ch.2) match (Output timer) Output compare (ch.3) match (Output timer) UART0 transmission complete I C interface 0 UART0 reception complete I C interface 1 Flash memory status Delayed interrupt generation module
2 2
Interrupt control registers ICR -- -- -- ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 Address -- -- -- 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H 0000B7H 0000B8H 0000B9H 0000BAH 0000BBH 0000BCH 0000BDH 0000BEH 0000BFH
x x x x
# 08 # 09 # 10 # 11 # 12 # 13 # 14 # 15
FFFFDCH FFFFD8H FFFFD4H FFFFD0H FFFFCCH FFFFC8H FFFFC4H FFFFC0H FFFFBCH FFFFB8H FFFFB4H FFFFB0H FFFFACH FFFFA8H FFFFA4H FFFFA0H FFFF9CH FFFF98H FFFF94H FFFF90H FFFF8CH FFFF88H FFFF84H FFFF80H FFFF7CH FFFF78H FFFF74H FFFF70H FFFF6CH FFFF68H FFFF64H FFFF60H FFFF5CH FFFF58H FFFF54H
x x x x
# 16 # 17 # 18 # 19 # 20 # 21 # 22 # 23 # 24 # 25 # 26 # 27
x
# 28 # 29 # 30 # 31 # 32 #33 # 34 # 35 # 36 # 37
x x x x
# 38 # 39 # 40 # 41 # 42
: The interrupt request flag is cleared by the EI2OS interrupt clear signal. x : The interrupt request flag is not cleared by the EI2OS interrupt clear signal. : The interrupt request flag is cleared by the EI2OS interrupt clear signal. The stop request is available.
28
MB90550A Series
Note: On using the EI2OS Function with Extended I/O Serial Interface 2 If a resource has two interrupt sources for the same interrupt number, both of the interrupt request flags are cleared by the EI2OS interrupt clear signal. When the EI2OS function is used for one of the two interrupt sources, therefore, the other interrupt function cannot be used. Set the interrupt request enable bit for the relevant resource to 0 for software polling processing. Interrupt source Extended I/O serial interface 1 16-bit free-run timer (I/O timer) overflow Interrupt No. # 23 # 24 ICR06 Interrupt control register Resource interrupt request Enabled Disabled
29
MB90550A Series
s ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(VSS = AVSS = 0.0 V) Parameter Symbol VCC Power supply voltage AVCC AVRH AVRL Input voltage Output voltage "L" level maximum output current*2 "L" level average output current "L" level total maximum output current "L" level total average output current "H" level maximum output current "H" level average output current "H" level total maximum output current "H" level total average output current Power consumption Operating temperature Storage temperature VI VO IOL1 IOL2 IOLAV1 IOLAV2 IOL IOLAV IOH*2 IOHAV*3 IOH IOHAV*4 PD TA TSTG Value Min. VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 -40 -55 Max. VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 VCC + 0.3 VCC + 0.3 10 20 4 12 150 80 -15 -4 -100 -50 500 +85 +150 Unit V V V V V V mA mA mA mA mA mA mA mA mA mA mW C C *5 *5 *5 Other than P20 to P27 P20 to P27 Other than P20 to P27 P20 to P27 VCC AVCC *1 AVCC AVRH AVRL Remarks
*1 : Be careful not to let AVcc exceed Vcc, for example, when the power supply is turned on. *2 : The maximum output current is a peak value for a corresponding pin. *3 : Average output current is an average current value observed for a 100 ms period for a corresponding pin. *4 : Total average current is an average current value observed for a 100 ms period for all corresponding pins. *5 : Average output current = operating current x operating efficiency WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
30
MB90550A Series
2. Recommended Operating Conditions
(VSS = AVSS = 0.0 V) Parameter Symbol Value Min. 4.5 Power supply voltage VCC AVCC VIH "H" level input voltage VIHS VIHM VIL "L" level input voltage Smoothing capacitor*4 Operating temperature VILS VILM CS TA 3.5 3.5 0.7VCC 0.8VCC VCC - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 0.1 -40 Max. 5.5 5.5 5.5 VCC+0.3 VCC+0.3 VCC+0.3 0.3VCC 0.2VCC VSS +0.3 1.0 +85 Unit V V V V V V V V V F C Remarks Normal operation (MB90F553A, MB90P553A, MB90V550A) Normal operation (MB90553A, MB90552A) Retains status at the time of operation stop CMOS input pin*1 CMOS hysteresys input pin*2 MD pin input*3 CMOS input pin*1 CMOS hysteresys input pin*2 MD pin input*3 *5
*1 : P00 to P07, P10 to P17, P20 to P27, P30 to P37 *2 : X0, HST, RST, P40 to P47, P50 to P55, P60 to P67, P70 to P77, P80 to P87, P90 to P97, PA0 to PA4 *3 : MD0, MD1, MD2 *4 : For connecting smoothing capacitor CS, see the diagram below: *5 : Use a ceramic capacitor or a capacitor with equivqlent frequency characteristics. The smoothing capacitor to be connected to the VCC pin must have a capacitance value higher than CS. * C pin connection circuit
C VSS AVSS
CS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 31
MB90550A Series
3. DC Characteristics
Parameter Open-drain output pin voltage "H" level output voltage "L" level output voltage 1 "L" level output voltage 2 Input leakage current Symbol Pin name
(VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Value Condition Unit Remarks Min. Typ. Max. -- VCC = 4.5V, IOH = -4.0mA VCC = 4.5V, IOL = 4.0mA VCC = 4.5V, IOL = 12.0mA VCC = 5.5V, VSS < VI < VCC Internal operation at 16 MHz VCC = 5.5 V Normal operation When data written in flash mode VSS - 0.3 VCC - 0.5 -- -- -5 -- -- -- -- -- -- -- -- -- -- -- -- 30 80 60 30 25 100 7 25 10 7 7 5 0.1 5 5 5 10 VSS + 6.0 -- 0.4 0.4 5 40 110 90 40 35 150 10 30 20 10 10 20 10 20 20 20 -- V V V V A mA mA mA mA mA mA mA mA mA mA mA A A A A A pF
MB90V550A MB90P553A MB90F553A MB90553A MB90552A MB90F553A MB90V550A MB90P553A MB90F553A MB90553A MB90552A MB90V550A MB90P553A MB90F553A MB90553A MB90552A
VD VOH VOL1 VOL2 IIL
P50 to P55 Other than P50 to P55 Other than P20 to P27 P20 to P27 All output pins
ICC
Power supply current*
VCC ICCS
Internal operation at 16 MHz VCC = 5.5 V In sleep mode
-- -- -- -- -- -- -- -- --
ICCH
VCC = 5.5V, TA = +25C In stop mode
Input capacitance Open-drain output leakage current Pull-up resistance
CIN
Other than AVCC, AVSS, C, VCC and VSS P50 to P55 P00 to P07 and P10 to P17 (In pull-up setting),RST
--
--
Ileak
--
-- 25
0.1 50 40
5 100 100
A k k Other than MB90V550A MB90V550A
RUP
-- 20
* : The current value is preliminary value and may be subject to change for enhanced characteristics without previous notice. The power supply current is measured with an external clock. 32
MB90550A Series
4. AC Characteristics
(1) Clock Timing (VCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Value Pin name Unit Unit Min. Typ. Max. X0, X1 X0, X1 -- X0 X0 -- 3 62.5 -- 10 -- 8.0 1.5 62.5 62.5 -- -- -- -- -- -- -- -- -- 16 333 5 -- 5 16 16 125 666 MHz ns % ns ns Recommended duty ratio of 40% to 60% External clock operation
Parameter Oscillation clock frequency Oscillation clock cycle time Frequency fluctuation rate locked* Input clock pulse width Input clock rising/falling time Internal operating clock frequency Internal operating clock cycle time
Symbol FC tC f PWH PWL tCR, tCF FCP
MHz PLL operation MHz When PLL is not used ns ns PLL operation When PLL is not used
tCP
--
* :The frequency fluctuation rate is the maximum deviation rate of the preset center frequency when the multiplied PLL signal is locked.
+ fo + x 100 (%)
f =
Center frequency
fo - -
* X0, X1 clock timing
tHCYL 0.8 VCC X0 PWH 0.8 VCC 0.2 VCC 0.2 VCC 0.8 VCC
tCF
PWL
tCR
33
MB90550A Series
* PLL operation guarantee range
Relationship between internal operating clock frequency and power supply voltage
Operation guarantee range MB90F553A, MB90P553A, MB90V550A
5.5
Power supply voltage VCC
4.5 3.5
PLL Operation guarantee range Operation guarantee range MB90553A, MB90552A
1.5
3
8
12
16
Internal operating clock frequency FCP (MHz) Relationship between oscillation clock frequency and internal operating clock frequency Internal operating clock frequency FCP (MHz)
Multiplied- Multipliedby-4 Multiplied-by-2 by-3
16
Multiplied-by-1
12 9 8
Not multiplied
4 1.5 3 4 8 16
Oscillation clock frequency FC (MHz)
The AC ratings are measured for the following measurement reference voltages * Input signal waveform
Hystheresis input pin
* Output signal waveform
Output pin
0.8 VCC 0.2 VCC
Pins other than hystheresis input/MD input
2.4 V 0.8 V
0.7 VCC 0.3 VCC
34
MB90550A Series
(2) Clock Output Timing
Parameter Cycle time CLK CLK time
Symbol tCYC tCHCL
(VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Value Pin name Unit Remarks Min. Max. CLK tCP tCP/2 - 20 -- tCP/2+20 ns ns
tCYC tCHCL 2.4 V 2.4 V 0.8 V
CLK
(3) Reset, Hardware Standby Input Timing
Parameter Reset input time Hardware standby input time
Symbol tRSTL tHSTL
(VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Value Pin name Unit Remarks Min. Max. RST HST 16 tCP 16 tCP -- -- ns ns
tRSTL, tHSTL
RST HST
0.2 VCC
0.2 VCC
35
MB90550A Series
(4) Specification for Power-on Reset
Parameter Power supply rising time Power-supply start voltage Power-supply end voltage Power supply cut-off time
Symbol tR VOFF VON tOFF
(VCC = 5.0 V 10 %, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Value Pin name Unit Remarks Min. Max. 0.066 VCC -- 3.5 4 30 0.2 -- -- ms V V ms Due to repeated operations
tR 3.5 V
VCC
0.2 V
0.2 V tOFF
0.2 V
Sudden changes in the power supply voltage may cause a power-on reset. To change the power supply voltage while the device is in operation, it is recommended to raise the voltage smoothly to suppress fluctuations as shown below. In this case, change the supply voltage with the PLL clock not used. If the voltage drop is 1 mV or fewer per second, however, you can use the PLL clock. VCC 5.0 V 3.5 V VSS 0V RAM data being held It is recommended to keep the rising speed of the supply voltage at 50 mV/ms or slower.
36
MB90550A Series
(5) Bus Read Timing
(VCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Symbol tLHLL tAVLL tLLAX tAVRL tAVDV tRLRH tRLDV tRHDX tRHLH tRHAX tAVCH tRLCH tLLRL ALE ALE, A23 to A16, AD15 to AD00 ALE, AD15 to AD00 A23 to A16, AD15 to AD00, RD A23 to A16, AD15 to AD00 RD RD, AD1 to AD00 RD, AD15 to AD00 RD, ALE ALE, A23 to A16 A23 to A16, AD15 to AD00, CLK RD, CLK ALE, RD Pin name Value Min. tCP/2 - 20 tCP/2 - 20 tCP/2 - 15 tCP - 15 -- 3 tCP/2 - 20 -- 0 tCP/2 - 15 tCP/2 - 10 tCP/2 - 20 tCP/2 - 20 tCP/2 - 15 -- -- -- 5 tCP/2 - 60 -- 3 tCP/2 - 60 -- -- -- -- -- -- Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Remarks
Parameter ALE pulse width Effective address ALE time ALE address effective time Effective address RD time Effective address valid data input RD pulse width RD valid data input RD data hold time RD ALE time RD address effective time Effective address CLK time RD CLK time ALE RD time
* Bus read timing
tAVCH 2.4 V tRLCH 2.4 V
CLK
tRHLH 2.4 V
ALE RD
tLHLL tAVLL
2.4 V 0.8 V tLLAX 0.8 V tRLDV tRLRH 2.4 V tRHAX 2.4 V 0.8 V tAVDV tRHDX 0.7 VCC 0.3 VCC
2.4 V
* Multiplex mode
tAVRL
tLLRL
A23 to A16
2.4 V 0.8 V
AD15 to AD00
2.4 V 0.8 V
Address
2.4 V 0.8 V
0.7 VCC 0.3 VCC
Read data
37
MB90550A Series
(6) Bus Write Timing
(VCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Symbol tAVWL tWLWH tDVWH tWHDX tWHAX tWHLH tWLCH Pin name A23 to A16, AD15 to AD00, WRH, WRL WRH, WRL AD15 to AD00, WRH, WRL AD15 to AD00, WRH, WRL A23 to A16, WRH, WRL WRH, WRL, ALE WRH, WRL, CLK Value Min. tCP - 15 3 tCP/2 - 20 3 tCP/2 - 20 20 tCP/2 - 10 tCP/2 - 15 tCP/2 - 20 Max. -- -- -- -- -- -- --
Unit
Parameter Effective address WR time WR pulse width valid data output WR time WR data hold time WR address effective time WR ALE time WR CLK time
Remarks
ns ns ns ns ns ns ns Multiplex mode
* Bus write timing
tWLCH 2.4 V
CLK
tWHLH 2.4 V
ALE
tAVWL tWLWH 2.4 V 0.8 V tWHAX 2.4 V 0.8 V tDVWH tWHDX 2.4 V 0.8 V 2.4 V 0.8 V
WR (WRL, WRH) * Multiplex mode
A23 to A16
AD15 to AD00
2.4 V 0.8 V
Address
2.4 V 0.8 V
Write data
38
MB90550A Series
(7) Ready Input Timing
(VCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Symbol tRYHS tRYHH Pin name RDY CLK Value Min. 45 0 Max. -- -- Unit ns ns Remarks
Parameter RDY setup time RDY hold time
Note : Use the automatic ready function when the setup time for the rising edge of the RDY signal is not sufficient. * Ready input timing
2.4 V CLK
ALE
WR (WRL, WRH)
0.8 V tRYHS tRYHH
RDY wait not inserted RDY wait inserted (1 cycle)
0.8 VCC
0.8 VCC
0.2 VCC
39
MB90550A Series
(8) Hold Timing
(VCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Parameter Symbol tXHAL tHAHV Pin name HAK Value Min. 30 tCP Max. tCP 2 tCP Unit ns ns Remarks
Pins in floating status HAK time HAK pin valid time
Note : More than 1 machine cycle is needed before HAK changes after HRQ pin is fetched.
* Hold timing
HAK
tXHAL
Pins High impedance
tHAHV
(9) UART, Extended I/O Sirial 0, 1 Timing
(VCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Pin name Condition Value Min. 8 tCP -80 100 tCP 4 tCP 4 tCP -- 60 60 Max. -- 80 -- -- -- -- 150 -- -- Unit ns ns ns ns ns ns ns ns ns Remarks
Parameter Serial clock cycle time SCK SOT delay time Valid SIN SCK SCK valid SIN hold time Serial clock "H" pulse width Serial clock "L" pulse width SCK SOT delay time Valid SIN SCK SCK valid SIN hold time
Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX
SCK0 to SCK2 SCK0 to SCK2, Internal shift clock SOT0 to SOT2 mode SCK0 to SCK2, CL = 80 pF + 1 TTL for an outSIN0 to SIN2 put pin SCK0 to SCK2, SIN0 to SIN2 SCK0 to SCK2 SCK0 to SCK2 External shift clock SCK0 to SCK2, mode SOT0 to SOT2 CL = 80 pF + 1 TTL for an SCK0 to SCK2, output pin SIN0 to SIN2 SCK0 to SCK2, SIN0 to SIN2
Notes: * These are AC ratings in the CLK synchronous mode. * CL is the load capacitance value connected to pins while testing.
40
MB90550A Series
* Internal shift clock mode
SCK
0.8 V tSLOV 2.4 V tSCYC 2.4 V 0.8 V
SOT
0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC
SIN
0.2 VCC
* External shift clock mode
SCK
0.2 VCC tSLOV 2.4 V tSLSH 0.8 VCC 0.2 VCC tSHSL 0.8 VCC
SOT
0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC
SIN
0.2 VCC
(10) Timer Input Timing (VCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Parameter Input pulse width Symbol tTIWH tTIWL Pin name TIN0, TIN1 IN0 to IN3 Value Min. 4 tCP Max. -- Unit ns Remarks
* Timer input timing
0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC
TIN0 to TIN1 IN0 to IN3
tTIWH
tTIWL
41
MB90550A Series
(11) Timer Output Timing
(VCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Symbol tTO Pin name TOT0,TOT1,OUT0, OUT1,PPG0 to PPG5 Value Min. 30 Max. -- Unit ns Remarks
Parameter CLK TOUT transition time
* Timer output timing
2.4 V
CLK
tTO
TOT0,TOT1 OUT0,OUT1 PPG0 to PPG5
2.4 V 0.8 V
(12) Trigger Input Timing
(VCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Symbol tTRGL Pin name IRQ0 to IRQ7 Value Min. 5 tCP Max. -- Unit ns Remarks
Parameter Input pulse width
* Trigger input timing
0.8 VCC
0.8 VCC 0.2 VCC tTRGH tTRGL 0.2 VCC
IRQ0 to IRQ7
42
MB90550A Series
(13) I2C Interface (VCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Symbol tCP tSTAO tSTOO tSTAI tSTOI tLOWO tHIGHO tDOO tDOSUO tLOWI tHIGHI tSUI tHOI SCL0 to SCL2 SDA0 to SDA2 SCL0 toSCL2 -- Pin name Value Min. 62.5 tCP (m x n/2 + 4) - 20 3 tCP + 40 3 tCP + 40 tCP (m x n/2 + 4) - 20 2 tCP - 20 4 tCP - 20 3 tCP + 40 tCP + 40 40 0 Max. 666 tCP (m x n/2 + 4) + 20 -- -- tCP (m x n/2 + 4) + 20 2 tCP + 20 -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Only as master Only as master Remarks All products
Parameter Internal clock cycle time Start condition output Stop condition output Start condition detection Stop condition detection SCL output "L" width SCL output "H" width SDA output delay time Setup after SDA output interrupt period SCL input "L" width SCL input "H" width SDA input setup time SDA input hold time
tCP x m x n/2 - 20 tCP x m x n/2 + 20
Only as slave
tCP x m x n/2 - 20 tCP x m x n/2 + 20
SDA0 to SDA2 SCL0 to SCL2 SCL0 to SCL2 SDA0 to SDA2 SCL0 to SCL2
Notes: * "m" and"n" in the above table represent the values of shift clock frequency setting bits (CS4 to CS0) in the clock control register "ICCR". For details, refer to the register description in the hardware manual. * tDOSUO represents the minimum value when the interrupt period is equal to or greater than the SCL "L" width. * The SDA and SCL output values indicate that that rise time is 0 ns.
43
MB90550A Series
* I2C interface [data transmitter (master/slave)]
tLOWO SCL 0.2 VCC 1 tSTAO tDOO 0.2 VCC 8 tDOO tSUI 9 tHOI tDOSUO tHIGHO 0.8 VCC 0.8 VCC 0.8 VCC 0.8 VCC 0.8 VCC
SDA
ACK
* I2C interface [data receiver (master/slave)]
tHIGHI 0.8 VCC SCL 0.2 VCC 6 tSUI 7 tHOI 0.2 VCC 8 0.2 VCC 9 tDOO tDOO tDOSUO 0.2 VCC tSTOI 0.8 VCC tLOWI 0.8 VCC
SDA
ACK
44
MB90550A Series
5. A/D Converter
(1)Electrical Characteristics (4.5 V AVRH - AVRL, VCC = AVCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Parameter Resolution Total error Non-linear error Differential linearity error Zero transition voltage Full-scale transition voltage Sampling period Compare time A/D Conversion time Analog port input current Analog input voltage Reference voltage Power supply current Reference voltage supply current Offset between channels Symbol Pin name -- -- -- -- VOT VFST tSMP tCMP tCNV IAIN VAIN -- -- IA IAH IR IRH -- -- -- -- -- AN0 to AN7 AN0 to AN7 -- -- -- AN0 to AN7 AN0 to AN7 AVRH AVRL AVCC AVRH AN0 to AN7 Value Min. -- -- -- -- AVRL- 3.5LSB AVRH- 6.5LSB 64 22 26.3 -- AVRL AVRL 0 -- -- -- -- -- Typ. 10 -- -- -- AVRL+ 0.5LSB AVRH- 1.5LSB -- -- -- -- -- -- -- 3.5 -- 300 -- -- Max. -- 5.0 2.5 1.9 AVRL+ 4.5LSB AVRH+ 1.5LSB 4096 -- -- 10 AVRH AVCC AVRH 7.0 5 500 5 4 Unit bit LSB LSB LSB
V V tCP s s A V V V mA A A A LSB
Remarks
1LSB= (AVRH-AVRL) /1024
*1 *2
*3 *3
*1: When FCP = 8 MHz, tCMP = 176 x tCP When FCP = 16 MHz, tCMP = 352 x tCP . . *2:Equivalent to the time for conversion per channel if "tSMP = 64 x tCP" or "tCMP = 352 x tCP" is selected when FCP = 16 MHz. *3:Specifies the power-supply current (Vcc = AVcc = AVRH = 5.0 V) when the A/D converter is inactive and the CPU has been stopped. Notes: * The error becomes larger relatively as |AVRH-AVRL| becomes smaller. * Use the output impedance rS of the external circuit for analog input under the following condition: External circuit output impedance rS = 10 k max. * If the output impedance of the external circuit is too high, the analog voltage sampling time may be insufficient. * If you insert a DC-blocking capacitor between the external circuit and the input pin, select the capacitance about several thousands times the sampling capacitance CSH in the chip to suppress the effect of capacity potential division with CSH.
45
MB90550A Series
* Analog input circuit model Microcontroller internal circuit
Input pin AN0
rS RSH CSH
Comparator Input pin AN7
VS
to
S/H circuit Analog channel selector
External circuit
rS = 10 k or less RSH = About 3 k CSH = About 25 pF Note: Device parameter values are provided as reference values for design purposes; they are not guaranteed.
46
MB90550A Series
(2) Definitions of Terms * Resolution: Analog transition identifiable by the A/D converter. Analog voltage can be divided into 1024 (210) components at 10-bit resolution. * Total error: Difference between actual and logical values. This error is the sum of an offset error, gain error, non-linearity error, and an error caused by noise. * Linearity error: Deviation of the straight line drawn between the zero transition point (00 0000 0000 <-> 00 0000 0001) and the full-scale transition point (11 1111 1110 <-> 11 1111 1111) of the device from actual conversion characteristics * Differential linearity error: Deviation from the ideal input voltage required to shift output code by one LSB
* 10-bit A/D converter conversion characteristics
11 11 11 11 1111 1111 1111 1111 * * * * 1LSB x N + VOT 1111 1110 1101 1100
Digital output
* * * * * * * * * 00 0000 0011 00 0000 0010 00 0000 0001 00 0000 0000 VOT VNT V(N + 1)T VFST
Linearity error
Analog input VFST - VOT 1022 VNT - (1LSB x N + VOT) Linearity error = [ LSB ] 1LSB V (N + 1) T - VNT - 1 [ LSB ] Differential linearity error = 1LSB 1LSB =
47
MB90550A Series
s EXAMPLE CHARACTERISTICS
1. "L" level output voltage
VOL - IOL Other than P20 to P27
700 600 500 VOL (mV) 400 300 200 100 0 0 2 4 IOL (mA) 6 8 10
VOL - IOL P20 to P27
700 TA = 25 C 600 500 VOL (mV) 400 300 200 100 0 0 5 10 15 IOL (mA) 20 25 30 VCC = 3.5 V VCC = 4.0 V VCC = 5.0 V VCC = 6.0 V
48
MB90550A Series
2. "H" level output voltage
(VCC - VOH) - IOH Other than P50 to P55
700 TA = 25 C 600 500 VCC - VOH (mV) 400 300 200 100 0 0 VCC = 3.5 V VCC = 4.0 V VCC = 5.0 V VCC = 6.0 V
-2
-4 IOH (mA)
-6
-8
-10
3. "H" level input voltage / "L" level input voltage (CMOS input)
VIH / VIL - VCC
5 4.5 4 3.5 VIH/VIL (V) 3 2.5 2 1.5 1 1.5 0 3.5
TA = 25 C
4
4.5 VCC (V)
5
5.5
49
MB90550A Series
4. "H" level input voltage / "L" level input voltage (CMOS hysteresis input)
VIHS / VILS - VCC
5 4.5 4 3.5 VIHS/VILS (V) 3 2.5 2 1.5 1 1.5 0 3.5
TA = 25 C
VIHS
VIHL
4
4.5 VCC (V)
5
5.5
50
MB90550A Series
5. Power supply current
(FCP = internal operating clock frequency) * MB90552A * Measurement conditions : External clock mode, ROM read loop operation, without resource operation, Typ. sample, internal operating frequency = 4MHz (external rectangular wave clock at 8MHz), TA = 25 C ICC - VCC
30
TA = 25 C FCP = 16 MHz
25 20 ICC (mA) 15
FCP = 10.6 MHz
FCP = 8 MHz 10 FCP = 4 MHz 5 0 3.5
4
4.5 VCC (V)
5
5.5
ICCS - VCC
10 9 8 7 ICCS (mA) 6 5 4 3 2 1
TA = 25 C FCP = 16 MHz
FCP = 10.6 MHz
FCP = 8 MHz
FCP = 4 MHz
0 3.5
4
4.5 VCC (V)
5
5.5
51
MB90550A Series
* MB90F553A * Measurement conditions : External clock mode, ROM read loop operation, without resource operation, Typ. sample, internal operating frequency = 4MHz (external rectangular wave clock at 8MHz), TA = 25 C ICC - VCC
70 60 50 ICC (mA) 40 30
TA = 25 C
FCP = 16 MHz
FCP = 10 MHz
FCP = 4 MHz 20 10 4.5
5 VCC (V)
5.5
ICCS - VCC
12 10
TA = 25 C FCP = 16 MHz
8 ICCS (mA) 6 4 FCP = 4MHz 2 0 4.5 FCP = 10 MHz
5 VCC (V)
5.5
52
MB90550A Series
6. Pull-up resistance
Pull-up resistance - VCC
90 80 TA = 85 C TA = 25 C 60 50 40 30 20 10 4 4.5 VCC (V) 5 5.5 TA = -40 C
Pull-up resistance (k)
70
53
MB90550A Series
s INSTRUCTIONS (340 INSTRUCTIONS)
Table 1 Item Mnemonic # ~ Explanation of Items in Tables of Instructions Meaning Upper-case letters and symbols: Represented as they appear in assembler. Lower-case letters: Replaced when described in assembler. Numbers after lower-case letters: Indicate the bit width within the instruction code. Indicates the number of bytes. Indicates the number of cycles. m : When branching n : When not branching See Table 4 for details about meanings of other letters in items. Indicates the number of accesses to the register during execution of the instruction. It is used calculate a correction value for intermittent operation of CPU. Indicates the correction value for calculating the number of actual cycles during execution of the instruction. (Table 5) The number of actual cycles during execution of the instruction is the correction value summed with the value in the "~" column. Indicates the operation of instruction. Indicates special operations involving the upper 8 bits of the lower 16 bits of the accumulator. Z : Transfers "0". X : Extends with a sign before transferring. - : Transfers nothing. Indicates special operations involving the upper 16 bits in the accumulator. * : Transfers from AL to AH. - : No transfer. Z : Transfers 00H to AH. X : Transfers 00H or FFH to AH by signing and extending AL. Indicates the status of each of the following flags: I (interrupt enable), S (stack), T (sticky bit), N (negative), Z (zero), V (overflow), and C (carry). * : Changes due to execution of instruction. - : No change. S : Set by execution of instruction. R : Reset by execution of instruction.
RG B
Operation LH
AH
I S T N Z V C
RMW
Indicates whether the instruction is a read-modify-write instruction. (a single instruction that reads data from memory, etc., processes the data, and then writes the result to memory.) * : Instruction is a read-modify-write instruction. - : Instruction is not a read-modify-write instruction. Note: A read-modify-write instruction cannot be used on addresses that have different meanings depending on whether they are read or written.
* Number of execution cycles The number of cycles required for instruction execution is acquired by adding the number of cycles for each instruction, a corrective value depending on the condition, and the number of cycles required for program fetch. Whenever the instruction being executed exceeds the two-byte (word) boundary, a program on an internal ROM connected to a 16-bit bus is fetched. If data access is interfered with, therefore, the number of execution cycles is increased. For each byte of the instruction being executed, a program on a memory connected to an 8-bit external data bus is fetched. If data access in interfered with, therefore, the number of execution cycles is increased. When a general-purpose register, an internal ROM, an internal RAM, an internal I/O device, or an external bus is accessed during intermittent CPU operation, the CPU clock is suspended by the number of cycles specified by the CG1/0 bit of the low-power consumption mode control register. When determining the number of cycles required for instruction execution during intermittent CPU operation, therefore, add the value of the number of times access is done x the number of cycles suspended as the corrective value to the number of ordinary execution cycles. 54
MB90550A Series
Table 2 Symbol A Explanation of Symbols in Tables of Instructions Meaning 32-bit accumulator The bit length varies according to the instruction. Byte : Lower 8 bits of AL Word : 16 bits of AL Long : 32 bits of AL and AH Upper 16 bits of A Lower 16 bits of A Stack pointer (USP or SSP) Program counter Program bank register Data bank register Additional data bank register System stack bank register User stack bank register Current stack bank register (SSB or USB) Direct page register DTB, ADB, SSB, USB, DPR, PCB, SPB DTB, ADB, SSB, USB, DPR, SPB R0, R1, R2, R3, R4, R5, R6, R7 RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7 RW0, RW1, RW2, RW3 RL0, RL1, RL2, RL3 Compact direct addressing Direct addressing Physical direct addressing Bit 0 to bit 15 of addr24 Bit 16 to bit 23 of addr24 I/O area (000000H to 0000FFH) 4-bit immediate data 8-bit immediate data 16-bit immediate data 32-bit immediate data 16-bit data signed and extended from 8-bit immediate data 8-bit displacement 16-bit displacement Bit offset Vector number (0 to 15) Vector number (0 to 255) Bit address PC relative addressing Effective addressing (codes 00 to 07) Effective addressing (codes 08 to 1F) Register list
AH AL SP PC PCB DTB ADB SSB USB SPB DPR brg1 brg2 Ri RWi RWj RLi dir addr16 addr24 ad24 0 to 15 ad24 16 to 23 io imm4 imm8 imm16 imm32 ext (imm8) disp8 disp16 bp vct4 vct8 ( )b rel ear eam rlst
55
MB90550A Series
Table 3 Code 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F R0 R1 R2 R3 R4 R5 R6 R7 Notation RW0 RW1 RW2 RW3 RW4 RW5 RW6 RW7 RL0 (RL0) RL1 (RL1) RL2 (RL2) RL3 (RL3) Effective Address Fields Address format Register direct "ea" corresponds to byte, word, and long-word types, starting from the left Number of bytes in address extension *
--
@RW0 @RW1 @RW2 @RW3 @RW0 + @RW1 + @RW2 + @RW3 + @RW0 + disp8 @RW1 + disp8 @RW2 + disp8 @RW3 + disp8 @RW4 + disp8 @RW5 + disp8 @RW6 + disp8 @RW7 + disp8 @RW0 + disp16 @RW1 + disp16 @RW2 + disp16 @RW3 + disp16 @RW0 + RW7 @RW1 + RW7 @PC + disp16 addr16
Register indirect 0 Register indirect with post-increment 0 Register indirect with 8-bit displacement 1
Register indirect with 16-bit displacement
2 0 0 2 2
Register indirect with index Register indirect with index PC indirect with 16-bit displacement Direct address
Note : The number of bytes in the address extension is indicated by the "+" symbol in the "#" (number of bytes) column in the tables of instructions.
56
MB90550A Series
Table 4 Code Number of Execution Cycles for Each Type of Addressing (a) Operand Ri RWi RLi @RWj @RWj + @RWi + disp8 @RWj + disp16 @RW0 + RW7 @RW1 + RW7 @PC + disp16 addr16 Number of execution cycles for each type of addressing Listed in tables of instructions 2 4 2 2 4 4 2 1 Number of register accesses for each type of addressing
00 to 07 08 to 0B 0C to 0F 10 to 17 18 to 1B 1C 1D 1E 1F
Listed in tables of instructions 1 2 1 1 2 2 0 0
Note : "(a)" is used in the "~" (number of states) column and column B (correction value) in the tables of instructions. Table 5 Compensation Values for Number of Cycles Used to Calculate Number of Actual Cycles Operand Internal register Internal memory even address Internal memory odd address Even address on external data bus (16 bits) Odd address on external data bus (16 bits) External data bus (8 bits) (b) byte
Cycles Access
(c) word
Cycles Access
(d) long
Cycles Access
+0 +0 +0 +1 +1 +1
1 1 1 1 1 1
+0 +0 +2 +1 +4 +4
1 1 2 1 2 2
+0 +0 +4 +2 +8 +8
2 2 4 2 4 4
Notes: * "(b)", "(c)", and "(d)" are used in the "~" (number of states) column and column B (correction value) in the tables of instructions. * When the external data bus is used, it is necessary to add in the number of wait cycles used for ready input and automatic ready. Table 6 Correction Values for Number of Cycles Used to Calculate Number of Program Fetch Cycles Instruction Internal memory External data bus (16 bits) External data bus (8 bits) Byte boundary -- -- +3 Word boundary +2 +3 --
Notes: * When the external data bus is used, it is necessary to add in the number of wait cycles used for ready input and automatic ready. * Because instruction execution is not slowed down by all program fetches in actuality, these correction values should be used for "worst case" calculations.
57
MB90550A Series
Table 7 Mnemonic MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVN MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV /MOV XCH XCH XCH XCH A, dir A, addr16 A, Ri A, ear A, eam A, io A, #imm8 A, @A A, @RLi+disp8 A, #imm4 A, dir A, addr16 A, Ri A, ear A, eam A, io A, #imm8 A, @A A,@RWi+disp8 A, @RLi+disp8 dir, A addr16, A Ri, A ear, A eam, A io, A @RLi+disp8, A Ri, ear Ri, eam ear, Ri eam, Ri Ri, #imm8 io, #imm8 dir, #imm8 ear, #imm8 eam, #imm8 @AL, AH @A, T A, ear A, eam Ri, ear Ri, eam # ~ Transfer Instructions (Byte) [41 Instructions]
RG
B (b) (b) 0 0 (b) (b) 0 (b) (b) 0 (b) (b) 0 0 (b) (b) 0 (b) (b) (b) (b) (b) 0 0 (b) (b) (b) 0 (b) 0 (b) 0 (b) (b) 0 (b) (b) 0 2x (b) 0 2x (b)
Operation byte (A) (dir) byte (A) (addr16) byte (A) (Ri) byte (A) (ear) byte (A) (eam) byte (A) (io) byte (A) imm8 byte (A) ((A)) byte (A) ((RLi)+disp8) byte (A) imm4 byte (A) (dir) byte (A) (addr16) byte (A) (Ri) byte (A) (ear) byte (A) (eam) byte (A) (io) byte (A) imm8 byte (A) ((A)) byte (A) ((RWi)+disp8) byte (A) ((RLi)+disp8) byte (dir) (A) byte (addr16) (A) byte (Ri) (A) byte (ear) (A) byte (eam) (A) byte (io) (A) byte ((RLi) +disp8) (A) byte (Ri) (ear) byte (Ri) (eam) byte (ear) (Ri) byte (eam) (Ri) byte (Ri) imm8 byte (io) imm8 byte (dir) imm8 byte (ear) imm8 byte (eam) imm8 byte ((A)) (AH) byte (A) (ear) byte (A) (eam) byte (Ri) (ear) byte (Ri) (eam)
LH AH
I
S
T
N
Z
V
C
RMW
3 2 4 3 2 1 2 2 2+ 3+ (a) 3 2 2 2 3 2 10 3 1 1 3 2 4 3 2 2 2 2 2+ 3+ (a) 3 2 2 2 3 2 5 2 10 3 2 3 1 2 2+ 2 3 2 2+ 2 2+ 2 3 3 3 3+ 2 3 4 2 2 3+ (a) 3 10 3 4+ (a) 4 5+ (a) 2 5 5 2 4+ (a) 3
0 0 1 1 0 0 0 0 2 0 0 0 1 1 0 0 0 0 1 2 0 0 1 1 0 0 2 2 1 2 1 1 0 0 1 0 0 2 0 4 2
Z Z Z Z Z Z Z Z Z Z
* * * * * * * - * *
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-* -* -* -* -* -* -* -* -* -R - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * - - * - * - - - -
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - * - * - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
X* X* X* X* X* X* X* X- X* X* - - - - - - - - - - - - - - - - - Z Z - - - - - - - - - - - - - - - - - - - - - - -
4 2 2+ 5+ (a) 7 2 2+ 9+ (a)
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
58
MB90550A Series
Table 8 Mnemonic MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW A, dir A, addr16 A, SP A, RWi A, ear A, eam A, io A, @A A, #imm16 A, @RWi+disp8 A, @RLi+disp8 # Transfer Instructions (Word/Long Word) [38 Instructions] ~
RG
B (c) (c) 0 0 0 (c) (c) (c) 0 (c) (c) (c) (c) 0 0 0 (c) (c) (c) (c) (0) (c) 0 (c) 0 (c) 0 (c) (c)
Operation word (A) (dir) word (A) (addr16) word (A) (SP) word (A) (RWi) word (A) (ear) word (A) (eam) word (A) (io) word (A) ((A)) word (A) imm16
LH AH
I
S
T
N
Z
V
C
RMW
2 3 3 4 1 1 1 2 2 2 2+ 3+ (a) 2 3 2 3 3 2 2 5 3 10 2 3 1 1 2 2+ 2 2 3 2 2+ 2 2+ 3 4 4 4+ 2 3 4 1 2 2 3+ (a) 3 5 10 3 4+ (a) 4 5+ (a) 2 5 2 4+ (a) 3
0 0 0 1 1 0 0 0 0 1 2 0 0 0 1 1 0 0 1 2 2 1 2 1 1 0 1 0 0
- - - - - - - - - word (A) ((RWi) +disp8) - word (A) ((RLi) +disp8) - word (dir) (A) word (addr16) (A) word (SP) (A) word (RWi) (A) word (ear) (A) word (eam) (A) word (io) (A) - - - - - - - word ((RWi) +disp8) (A) - word ((RLi) +disp8) (A) - word (RWi) (ear) - word (RWi) (eam) - word (ear) (RWi) - word (eam) (RWi) - word (RWi) imm16 - word (io) imm16 - word (ear) imm16 - word (eam) imm16 - word ((A)) (AH) word (A) (ear) word (A) (eam) word (RWi) (ear) word (RWi) (eam) long (A) (ear) long (A) (eam) long (A) imm32 long (ear) (A) long (eam) (A) - - - - - - - - - -
* * * * * * * - * * * - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
* * * * * * * * * * * * * * * * * * * * * * * * * - * - * - - - - * * * * *
* * * * * * * * * * * * * * * * * * * * * * * * * - * - * - - - - * * * * *
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MOVW dir, A MOVW addr16, A MOVW SP A , MOVW RWi, A MOVW ear, A MOVW eam, A MOVW io, A MOVW @RWi+disp8, A MOVW @RLi+disp8, A MOVW RWi, ear MOVW RWi, eam MOVW ear, RWi MOVW eam, RWi MOVW RWi, #imm16 MOVW io, #imm16 MOVW ear, #imm16 MOVW eam, #imm16 MOVW @AL, AH /MOVW@A, T XCHW XCHW XCHW XCHW A, ear A, eam RWi, ear RWi, eam
2 4 2+ 5+ (a) 2 7 2+ 9+ (a) 2 4 2+ 5+ (a) 5 3 2 4 2+ 5+ (a)
2 0 0 2x (c) 4 0 2 2x (c) 2 0 0 2 0 0 (d) 0 0 (d)
MOVL A, ear MOVL A, eam MOVL A, #imm32 MOVL ear, A MOVL eam, A
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
59
MB90550A Series
Table 9 Mnemonic ADD ADD ADD ADD ADD ADD ADDC ADDC ADDC ADDDC SUB SUB SUB SUB SUB SUB SUBC SUBC SUBC SUBDC A,#imm8 A, dir A, ear A, eam ear, A eam, A A A, ear A, eam A A, #imm8 A, dir A, ear A, eam ear, A eam, A A A, ear A, eam A Addition and Subtraction Instructions (Byte/Word/Long Word) [42 Instructions] # 2 2 2 2+ 2 2+ 1 2 2+ 1 2 2 2 2+ 2 2+ 1 2 2+ 1 1 2 2+ 3 2 2+ 2 2+ 1 2 2+ 3 2 2+ 2 2+ ~ 2 5 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 2 5 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 2 3 4+ (a) 2 3 5+ (a) 3 4+ (a) 2 3 4+ (a) 2 3 5+ (a) 3 4+ (a)
RG
B 0 (b) 0 (b) 0 2x (b) 0 0 (b) 0 0 (b) 0 (b) 0 2x (b) 0 0 (b) 0 0 0 (c) 0 0 2x (c) 0 (c) 0 0 (c) 0 0 2x (c) 0 (c) 0 (d) 0 0 (d) 0
Operation byte (A) (A) +imm8 byte (A) (A) +(dir) byte (A) (A) +(ear) byte (A) (A) +(eam) byte (ear) (ear) + (A) byte (eam) (eam) + (A) byte (A) (AH) + (AL) + (C) byte (A) (A) + (ear) + (C) byte (A) (A) + (eam) + (C)
LH AH
I
S
T
N
Z
V
C
RMW
0 0 1 0 2 0 0 1 0 0 0 0 1 0 2 0 0 1 0 0 0 1 0 0 2 0 1 0 0 1 0 0 2 0 1 0 2 0 0 2 0 0
Z Z Z Z - Z Z Z Z byte (A) (AH) + (AL) + (C) (decimal) Z Z byte (A) (A) -imm8 Z byte (A) (A) - (dir) Z byte (A) (A) - (ear) Z byte (A) (A) - (eam) - byte (ear) (ear) - (A) - byte (eam) (eam) - (A) byte (A) (AH) - (AL) - (C) Z byte (A) (A) - (ear) - (C) Z byte (A) (A) - (eam) - (C) Z byte (A) (AH) - (AL) - (C) (decimal) Z word (A) (AH) + (AL) word (A) (A) +(ear) word (A) (A) +(eam) word (A) (A) +imm16 word (ear) (ear) + (A) word (eam) (eam) + (A) word (A) (A) + (ear) + (C) word (A) (A) + (eam) + (C) word (A) (AH) - (AL) word (A) (A) - (ear) word (A) (A) - (eam) word (A) (A) -imm16 word (ear) (ear) - (A) word (eam) (eam) - (A) word (A) (A) - (ear) - (C) word (A) (A) - (eam) - (C) long (A) (A) + (ear) long (A) (A) + (eam) long (A) (A) +imm32 long (A) (A) - (ear) long (A) (A) - (eam) long (A) (A) -imm32 - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
- - - - - * - - - - - - - - - * - - - - - - - - - * - - - - - - - * - - - - - - - -
ADDW A ADDW A, ear ADDW A, eam ADDW A, #imm16 ADDW ear, A ADDW eam, A ADDCW A, ear ADDCW A, eam SUBW A SUBW A, ear SUBW A, eam SUBW A, #imm16 SUBW ear, A SUBW eam, A SUBCW A, ear SUBCW A, eam ADDL ADDL ADDL SUBL SUBL SUBL
A, ear 2 6 A, eam 2+ 7+ (a) A, #imm32 5 4 A, ear 2 6 A, eam 2+ 7+ (a) A, #imm32 5 4
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
60
MB90550A Series
Table 10 Mnemonic INC INC DEC DEC INCW INCW ear eam ear eam ear eam Increment and Decrement Instructions (Byte/Word/Long Word) [12 Instructions] # ~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
2 2 2+ 5+ (a) 2 3 2+ 5+ (a) 2 3 2+ 5+ (a) 2 3 2+ 5+ (a) 2 7 2+ 9+ (a) 2 7 2+ 9+ (a)
2 0 2 0 2 0 2 0 4 0 4 0
0 byte (ear) (ear) +1 2x (b) byte (eam) (eam) +1 0 byte (ear) (ear) -1 2x (b) byte (eam) (eam) -1 0 word (ear) (ear) +1 2x (c) word (eam) (eam) +1 0 word (ear) (ear) -1 2x (c) word (eam) (eam) -1 0 long (ear) (ear) +1 2x (d) long (eam) (eam) +1 0 long (ear) (ear) -1 2x (d) long (eam) (eam) -1
- - - - - - - - - - - -
- - - - - - - - - - - -
- - - - - - - - - - - -
- - - - - - - - - - - -
- - - - - - - - - - - -
* * * * * * * * * * * *
* * * * * * * * * * * *
* * * * * * * * * * * *
- - - - - - - - - - - -
- * - * - * - * - * - *
DECW ear DECW eam INCL INCL DECL DECL ear eam ear eam
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." Table 11 Mnemonic CMP CMP CMP CMP CMPW CMPW CMPW CMPW CMPL CMPL CMPL A A, ear A, eam A, #imm8 # 1 2 2+ 2 Compare Instructions (Byte/Word/Long Word) [11 Instructions] ~ 1 2 3+ (a) 2 1 2 3+ (a) 2 6 7+ (a) 3
RG
B 0 0 (b) 0 0 0 (c) 0 0 (d) 0
Operation byte (AH) - (AL) byte (A) (ear) byte (A) (eam) byte (A) imm8 word (AH) - (AL) word (A) (ear) word (A) (eam) word (A) imm16 word (A) (ear) word (A) (eam) word (A) imm32
LH
AH
I
S
T
N
Z
V
C
RMW
0 1 0 0 0 1 0 0 2 0 0
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
* * * * * * * * * * *
* * * * * * * * * * *
* * * * * * * * * * *
* * * * * * * * * * *
- - - - - - - - - - -
A 1 A, ear 2 A, eam 2+ A, #imm16 3 A, ear 2 A, eam 2+ A, #imm32 5
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
61
MB90550A Series
Table 12 Mnemonic DIVU DIVU DIVU A A, ear Multiplication and Division Instructions (Byte/Word/Long Word) [11 Instructions] # 1 2 ~ *
1
RG
B
Operation
Quotient byte (AL) Remainder byte (AH) Quotient byte (A) Remainder byte (ear) Quotient byte (A) Remainder byte (eam) Quotient word (A) Remainder word (ear) Quotient word (A) Remainder word (ear)
LH AH
I
S
T
N
Z
V
C
RMW
0 1 0 1 0
0 word (AH) /byte (AL) 0 word (A)/byte (ear)
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
* * * * * - - - - - -
* * * * * - - - - - -
- - - - - - - - - - -
*2
A, eam 2+ *3 2 *4
*6 word (A)/byte (eam) 0 long (A)/word (ear)
DIVUW A, ear
DIVUW A, eam 2+ *5 MULU MULU MULU A 1 *8 A, ear 2 *9 A, eam 2+ *10
*7 long (A)/word (eam)
0 0 byte (AH) *byte (AL) word (A) 1 0 byte (A) *byte (ear) word (A) 0 (b) byte (A) *byte (eam) word (A) 0 0 word (AH) *word (AL) long (A) 1 0 word (A) *word (ear) long (A) 0 (c) word (A) *word (eam) long (A)
MULUW A 1 *11 MULUW A, ear 2 *12 MULUW A, eam 2+ *13 *1: *2: *3: *4: *5: *6: *7: *8: *9: *10: *11: *12: *13:
3 when the result is zero, 7 when an overflow occurs, and 15 normally. 4 when the result is zero, 8 when an overflow occurs, and 16 normally. 6 + (a) when the result is zero, 9 + (a) when an overflow occurs, and 19 + (a) normally. 4 when the result is zero, 7 when an overflow occurs, and 22 normally. 6 + (a) when the result is zero, 8 + (a) when an overflow occurs, and 26 + (a) normally. (b) when the result is zero or when an overflow occurs, and 2 x (b) normally. (c) when the result is zero or when an overflow occurs, and 2 x (c) normally. 3 when byte (AH) is zero, and 7 when byte (AH) is not zero. 4 when byte (ear) is zero, and 8 when byte (ear) is not zero. 5 + (a) when byte (eam) is zero, and 9 + (a) when byte (eam) is not 0. 3 when word (AH) is zero, and 11 when word (AH) is not zero. 4 when word (ear) is zero, and 12 when word (ear) is not zero. 5 + (a) when word (eam) is zero, and 13 + (a) when word (eam) is not zero.
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
62
MB90550A Series
Table 13 Signed Multiplication and Division Instructions (Byte/Word/Long Word) [11 Instructions] # 2 2 ~ *1 *2 *3 *4 *5
RG
Mnemonic DIV DIV DIV DIVW DIVW A A, ear
B 0
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
0 1 0 1 0
A, eam 2 + A, ear A, eam 2 2+
word (AH) /byte (AL) Quotient byte (AL) Remainder byte (AH) 0 word (A)/byte (ear) Quotient byte (A) Remainder byte (ear) *6 word (A)/byte (eam) Quotient byte (A) Remainder byte (eam) 0 long (A)/word (ear) Quotient word (A) Remainder word (ear) *7 long (A)/word (eam) Quotient word (A) Remainder word (eam) 0 0 (b) 0 0 (c) byte (AH) *byte (AL) word (A) byte (A) *byte (ear) word (A) byte (A) *byte (eam) word (A) word (AH) *word (AL) long (A) word (A) *word (ear) long (A) word (A) *word (eam) long (A)
Z Z Z - -
- - - - -
- - - - -
- - - - -
- - - - -
- - - - -
- - - - -
* * * * *
* * * * *
- - - - -
MULU MULU MULU MULUW MULUW MULUW *1: *2: *3: *4:
A 2 A, ear 2 A, eam 2 + A 2 A, ear 2 A, eam 2 +
*8 *9 *10 *11 *12 *13
0 1 0 0 1 0
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
Set to 3 when the division-by-0, 8 or 18 for an overflow, and 18 for normal operation. Set to 3 when the division-by-0, 10 or 21 for an overflow, and 22 for normal operation. Set to 4 + (a) when the division-by-0, 11 + (a) or 22 + (a) for an overflow, and 23 + (a) for normal operation. Positive dividend: Set to 4 when the division-by-0, 10 or 29 for an overflow, and 30 for normal operation. Negative dividend: Set to 4 when the division-by-0, 11 or 30 for an overflow and 31 for normal operation. *5: Positive dividend: Set to 4 + (a) when the division-by-0, 11 + (a) or 30 + (a) for an overflow, and 31 + (a) for normal operation. Negative dividend: Set to 4 + (a) when the division-by-0, 12 + (a) or 31 + (a) for an overflow, and 32 + (a) for normal operation. *6: When the division-by-0, (b) for an overflow, and 2 x (b) for normal operation. *7: When the division-by-0, (c) for an overflow, and 2 x (c) for normal operation. *8: Set to 3 when byte (AH) is zero, 12 when the result is positive, and 13 when the result is negative. *9: Set to 3 when byte (ear) is zero, 12 when the result is positive, and 13 when the result is negative. *10: Set to 4 + (a) when byte (eam) is zero, 13 + (a) when the result is positive, and 14 + (a) when the result is negative. *11: Set to 3 when word (AH) is zero, 12 when the result is positive, and 13 when the result is negative. *12: Set to 3 when word (ear) is zero, 16 when the result is positive, and 19 when the result is negative. *13: Set to 4 + (a) when word (eam) is zero, 17 + (a) when the result is positive, and 20 + (a) when the result is negative. Notes: * When overflow occurs during DIV or DIVW instruction execution, the number of execution cycles takes two values because of detection before and after an operation. * When overflow occurs during DIV or DIVW instruction execution, the contents of AL are destroyed. * For (a) to (d), refer to "Table 4 Number of Execution Cycles for Effective Address in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles."
63
MB90550A Series
Table 14 Mnemonic AND AND AND AND AND OR OR OR OR OR XOR XOR XOR XOR XOR NOT NOT NOT ANDW ANDW ANDW ANDW ANDW ANDW ORW ORW ORW ORW ORW ORW XORW XORW XORW XORW XORW XORW A, #imm8 A, ear A, eam ear, A eam, A A, #imm8 A, ear A, eam ear, A eam, A A, #imm8 A, ear A, eam ear, A eam, A A ear eam # ~ Logical 1 Instructions (Byte/Word) [39 Instructions]
RG
B 0 0 (b) 0 2x (b) 0 0 (b) 0 2x (b) 0 0 (b) 0 2x (b)
Operation byte (A) (A) and imm8 byte (A) (A) and (ear) byte (A) (A) and (eam) byte (ear) (ear) and (A) byte (eam) (eam) and (A) byte (A) (A) or imm8 byte (A) (A) or (ear) byte (A) (A) or (eam) byte (ear) (ear) or (A) byte (eam) (eam) or (A) byte (A) (A) xor imm8 byte (A) (A) xor (ear) byte (A) (A) xor (eam) byte (ear) (ear) xor (A) byte (eam) (eam) xor (A)
LH AH
I
S
T
N
Z
V
C
RMW
2 2 2 3 2+ 4+ (a) 2 3 2+ 5+ (a) 2 2 2 3 2+ 4+ (a) 2 3 2+ 5+ (a) 2 2 2 3 2+ 4+ (a) 2 3 2+ 5+ (a) 1 2 2 3 2+ 5+ (a)
0 1 0 2 0 0 1 0 2 0 0 1 0 2 0 0 2 0 0 0 1 0 2 0 0 0 1 0 2 0 0 0 1 0 2 0 0 2 0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - * - - - - * - - - - * - - * - - - - - * - - - - - * - - - - - * - - *
0 byte (A) not (A) 0 byte (ear) not (ear) 2x (b) byte (eam) not (eam) 0 0 0 (c) 0 2x (c) 0 0 0 (c) 0 2x (c) 0 0 0 (c) 0 2x (c) word (A) (AH) and (A) word (A) (A) and imm16 word (A) (A) and (ear) word (A) (A) and (eam) word (ear) (ear) and (A) word (eam) (eam) and (A) word (A) (AH) or (A) word (A) (A) or imm16 word (A) (A) or (ear) word (A) (A) or (eam) word (ear) (ear) or (A) word (eam) (eam) or (A) word (A) (AH) xor (A) word (A) (A) xor imm16 word (A) (A) xor (ear) word (A) (A) xor (eam) word (ear) (ear) xor (A) word (eam) (eam) xor (A)
A 1 2 A, #imm16 3 2 A, ear 2 3 A, eam 2+ 4+ (a) ear, A 2 3 eam, A 2+ 5+ (a) A 1 2 A, #imm16 3 2 A, ear 2 3 A, eam 2+ 4+ (a) ear, A 2 3 eam, A 2+ 5+ (a) A 1 2 A, #imm16 3 2 A, ear 2 3 A, eam 2+ 4+ (a) ear, A 2 3 eam, A 2+ 5+ (a) 1 2 2 3 2+ 5+ (a)
NOTW A NOTW ear NOTW eam
0 word (A) not (A) 0 word (ear) not (ear) 2x (c) word (eam) not (eam)
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
64
MB90550A Series
Table 15 Mnemonic ANDL A, ear ANDL A, eam ORL ORL A, ear A, eam # 2 2+ 2 2+ 2 2+ ~ 6 7+ (a) 6 7+ (a) 6 7+ (a) Logical 2 Instructions (Long Word) [6 Instructions]
RG
B 0 (d) 0 (d) 0 (d)
Operation long (A) (A) and (ear) long (A) (A) and (eam) long (A) (A) or (ear) long (A) (A) or (eam) long (A) (A) xor (ear) long (A) (A) xor (eam)
LH
AH
I
S
T
N
Z
V
C
RMW
2 0 2 0 2 0
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
* * * * * *
* * * * * *
R R R R R R
- - - - - -
- - - - - -
XORL A, ea XORL A, eam
Table 16 Mnemonic NEG NEG NEG A ear eam # 1 ~ 2
Sign Inversion Instructions (Byte/Word) [6 Instructions]
RG
B 0
Operation byte (A) 0 - (A)
LH
AH
I
S
T
N
Z
V
C
RMW
0 2 0 0 2 0
X - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
* * * * * *
* * * * * *
* * * * * *
* * * * * *
- - * - - *
2 3 2+ 5+ (a) 1 2
0 byte (ear) 0 - (ear) 2x (b) byte (eam) 0 - (eam) 0 word (A) 0 - (A)
NEGW A NEGW ear NEGW eam
2 3 2+ 5+ (a)
0 word (ear) 0 - (ear) 2x (c) word (eam) 0 - (eam)
Table 17 Mnemonic NRML A, R0 # 2 ~ *1 RG 1 B 0
Normalize Instruction (Long Word) [1 Instruction] Operation
LH AH I S T N Z V C RMW
long (A) Shift until first digit is "1" - byte (R0) Current shift count
-
-
-
-
-
*
-
-
-
*1: 4 when the contents of the accumulator are all zeroes, 6 + (R0) in all other cases (shift count). Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
65
MB90550A Series
Table 18 Mnemonic
RORC A ROLC A RORC ear RORC eam ROLC ear ROLC eam ASR LSR LSL A, R0 A, R0 A, R0
Shift Instructions (Byte/Word/Long Word) [18 Instructions]
RG
# 2 2
~ 2 2
B 0 0
Operation
byte (A) Right rotation with carry byte (A) Left rotation with carry byte (ear) Right rotation with carry byte (eam) Right rotation with carry byte (ear) Left rotation with carry byte (eam) Left rotation with carry
byte (A) Arithmetic right barrel shift (A, R0) byte (A) Logical right barrel shift (A, R0) byte (A) Logical left barrel shift (A, R0) word (A) Arithmetic right shift (A, 1 bit)
LH AH
I
S
T
N
Z
V
C
RMW
0 0
- - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - -
--- --- - - - - - - - - - - - -
* * * * * * * * *
* * * * * * * * *
- - - - - - - - - - - - - - - - - -
* * * * * * * * * * * * * * * * * *
- - - * - * - - - - - - - - - - - -
2 3 2+ 5+ (a) 2 3 2+ 5+ (a) 2 2 2 1 1 1 2 2 2 2 2 2 *1 *1 *1 2 2 2 *1 *1 *1 *2 *2 *2
2 0 0 2x (b) 2 0 0 2x (b) 1 1 1 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
--* --* ---
ASRW A LSRW A/SHRW A LSLW A/SHLW A ASRW A, R0 LSRW A, R0 LSLW A, R0 ASRL A, R0 LSRL A, R0 LSLL A, R0
word (A) Logical right shift (A, 1 bit) word (A) Logical left shift (A, 1 bit)
word (A) Arithmetic right barrel shift (A, R0) word (A) Logical right barrel shift (A, R0) word (A) Logical left barrel shift (A, R0) long (A) Logical right barrel shift (A, R0) long (A) Logical left barrel shift (A, R0)
--*** --*R* ---** --* --* --- --* --* --- * * * * * * * * * * * *
long (A) Arithmetic right shift (A, R0) -
- -
*1: 6 when R0 is 0, 5 + (R0) in all other cases. *2: 6 when R0 is 0, 6 + (R0) in all other cases. Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
66
MB90550A Series
Table 19 Mnemonic BZ/BEQ BNZ/BNE BC/BLO BNC/BHS BN rel BP rel BV rel BNV rel BT rel BNT rel BLT rel BGE rel BLE rel BGT rel BLS rel BHI rel BRA rel JMP JMP JMP JMP JMPP JMPP JMPP CALL CALL CALL CALLV CALLP rel rel rel rel # 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 3 2 2+ 2 2+ 4 ~ * *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 2 3 3 4+ (a) 5 6+ (a) 4 6 7+ (a) 6 7 10
1
Branch 1 Instructions [31 Instructions] B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (c) 0 (d) 0 Operation Branch when (Z) = 1 Branch when (Z) = 0 Branch when (C) = 1 Branch when (C) = 0 Branch when (N) = 1 Branch when (N) = 0 Branch when (V) = 1 Branch when (V) = 0 Branch when (T) = 1 Branch when (T) = 0 Branch when (V) xor (N) = 1 Branch when (V) xor (N) = 0
Branch when ((V) xor (N)) or (Z) = 1 Branch when ((V) xor (N)) or (Z) = 0
LH AH I S T N Z V C RMW
RG
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 0 0 1 0 0 0 2 0 0
Branch when (C) or (Z) = 1 Branch when (C) or (Z) = 0 Branch unconditionally word (PC) (A) word (PC) addr16 word (PC) (ear) word (PC) (eam)
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
@A addr16 @ear @eam @ear *3 @eam *3 addr24
word (PC) (ear), (PCB) (ear +2) word (PC) (eam), (PCB) (eam +2)
2 @ear *4 @eam *4 2+ addr16 *5 3 1 #vct4 *5 2 @ear *6
(c) 2x (c) (c) 2x (c) 2x (c) *2 2x (c)
CALLP @eam *6 CALLP addr24 *7 *1: *2: *3: *4: *5: *6: *7:
2+ 11+ (a) 4 10
word (PC) ad24 0 to 15, (PCB) ad24 16 to 23 word (PC) (ear) word (PC) (eam) word (PC) addr16 Vector call instruction word (PC) (ear) 0 to 15, (PCB) (ear) 16 to 23 word (PC) (eam) 0 to 15, (PCB) (eam) 16 to 23 word (PC) addr0 to 15, (PCB) addr16 to 23
4 when branching, 3 when not branching. (b) + 3 x (c) Read (word) branch address. W: Save (word) to stack; R: read (word) branch address. Save (word) to stack. W: Save (long word) to W stack; R: read (long word) R branch address. Save (long word) to stack.
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
67
MB90550A Series
Table 20 Mnemonic CBNE A, #imm8, rel CWBNE A, #imm16, rel CBNE
CBNE
Branch 2 Instructions [19 Instructions] B 0 0 0 (b) 0 (c) 0 Operation
Branch when byte (A) imm8 Branch when word (A) imm16 Branch when byte (ear) imm8 Branch when byte (eam) imm8 Branch when word (ear) imm16 Branch when word (eam) imm16
LH AH I S T N Z V C RMW
# 3 4
10
~ * *1 *2 *3 *4 *3 *5
1
RG
0 0 1 0 1 0 2
- - - - - - - - - - - - - - - -
----* ----* - - - - - - - - - - - - - - - - * * * *
* * * * * * * * * * - - - - *
* * * * * *
* * * * * *
- - - - - - - * - * - - - - - -
ear, #imm8, rel
eam, #imm8, rel*
CWBNE ear, #imm16, rel
CWBNE eam, #imm16, rel*10
4 4+ 5 5+ 3
DBNZ DBNZ
ear, rel eam, rel
3+ *6 3 *5
Branch when byte (ear) = (ear) - 1, and (ear) 0 2 2x (b) Branch when byte (eam) = (eam) - 1, and (eam) 0 2 2 0 0 0 0 0 0 Branch when word (ear) = (ear) - 1, and (ear) 0 2x (c) Branch when word (eam) = (eam) - 1, and (eam) 0 8x (c) 6x (c) 6x (c) 8x (c) *7 (c) Software interrupt Software interrupt Software interrupt Software interrupt Return from interrupt At constant entry, save old frame pointer to stack, set new frame pointer, and allocate local pointer area At constant entry, retrieve old frame pointer from stack. Return from subroutine Return from subroutine 0
----* ----* ----* ----* - - - - - R R R R * S S S S * - - - - * - - - - *
*- *- *- *- - - - - * - - - - *
DWBNZ ear, rel DWBNZ eam, rel INT INT INTP INT9 RETI LINK #vct8 addr16 addr24
3+ *6 2 3 4 1 1 2 20 16 17 20 15 6
#local8
--------
UNLINK RET *8 RETP *9
1 1 1
5 4 6
0 0 0
(c) (c) (d)
- - -
-------- -------- --------
- - -
*1: 5 when branching, 4 when not branching *2: 13 when branching, 12 when not branching *3: 7 + (a) when branching, 6 + (a) when not branching *4: 8 when branching, 7 when not branching *5: 7 when branching, 6 when not branching *6: 8 + (a) when branching, 7 + (a) when not branching *7: Set to 3 x (b) + 2 x (c) when an interrupt request occurs, and 6 x (c) for return. *8: Retrieve (word) from stack *9: Retrieve (long word) from stack *10: In the CBNE/CWBNE instruction, do not use the RWj+ addressing mode. Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
68
MB90550A Series
Table 21 Mnemonic PUSHW A PUSHW AH PUSHW PS PUSHW rlst POPW POPW POPW POPW JCTX A AH PS rlst @A # 1 1 1 2 1 1 1 2 1 2 2 2 2 Other Control Instructions (Byte/Word/Long Word) [36 Instructions] ~ 4 4 4 *3 3 3 4 *2 14 3 3 2 2
RG
B (c) (c) (c) *4 (c) (c) (c) *4
Operation
word (SP) (SP) -2, ((SP)) (A) word (SP) (SP) -2, ((SP)) (AH) word (SP) (SP) -2, ((SP)) (PS) (SP) (SP) -2n, ((SP)) (rlst) word (A) ((SP)), (SP) (SP) +2 word (AH) ((SP)), (SP) (SP) +2 word (PS) ((SP)), (SP) (SP) +2 (rlst) ((SP)), (SP) (SP) +2n
LH AH
I
S
T
N
Z
V
C
RMW
0 0 0 *5 0 0 0 *5 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
- - - - - - - - -
- - - - * - - - - - - - - - - * * - -
- - - -
- - - -
- - - -
- - - -
- - - -
- - - -
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - -
------- ------- ******* ------- * * * * * * * * * * * * * * * * * * * * *
6x (c) Context switch instruction 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
AND CCR, #imm8 OR CCR, #imm8 MOV RP #imm8 , MOV ILM, #imm8
byte (CCR) (CCR) and imm8 - - byte (CCR) (CCR) or imm8 byte (RP) imm8 byte (ILM) imm8 word (RWi) ear word (RWi) eam word(A) ear word (A) eam word (SP) (SP) +ext (imm8) word (SP) (SP) +imm16 byte (A) (brgl) byte (brg2) (A) No operation
Prefix code for accessing AD space Prefix code for accessing DT space Prefix code for accessing PC space Prefix code for accessing SP space
- - - - - - - -
------- ------- - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MOVEA RWi, ear 2 3 MOVEA RWi, eam 2+ 2+ (a) MOVEA A, ear 2 1 MOVEA A, eam 2+ 1+ (a) ADDSP #imm8 ADDSP #imm16 MOV MOV NOP ADB DTB PCB SPB NCC CMR A, brgl brg2, A 2 3 2 2 1 1 1 1 1 1 1 3 3 *1 1 1 1 1 1 1 1 1
------- ------- --- --- - - - - - - - - - - - - - - - - - - - - - * * - - - - - - - * * - - - - - - - -- -- - - - - - - - - - - - - - -
Z* -- - - - - - - - - - - - - - -
Prefix code for no flag change
Prefix code for common register bank
*1: PCB, ADB, SSB, USB, and SPB : 1 state DTB, DPR : 2 states *2: 7 + 3 x (pop count) + 2 x (last register number to be popped), 7 when rlst = 0 (no transfer register) *3: 29 + (push count) - 3 x (last register number to be pushed), 8 when rlst = 0 (no transfer register) *4: Pop count x (c), or push count x (c) *5: Pop count or push count. Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
69
MB90550A Series
Table 22 Mnemonic MOVB A, dir:bp MOVB A, addr16:bp MOVB A, io:bp MOVB dir:bp, A MOVB addr16:bp, A MOVB io:bp, A SETB dir:bp SETB addr16:bp SETB io:bp CLRB dir:bp CLRB addr16:bp CLRB io:bp BBC BBC BBC BBS BBS BBS dir:bp, rel addr16:bp, rel io:bp, rel dir:bp, rel addr16:bp, rel io:bp, rel # 3 4 3 3 4 3 3 4 3 3 4 3 4 5 4 4 5 4 5 3 3 ~ 5 5 4 7 7 6 7 7 7 7 7 7 *1 *1 *2 *1 *1 *2 *3 *4 *4
RG
Bit Manipulation Instructions [21 Instructions] B (b) (b) (b) Operation byte (A) (dir:bp) b byte (A) (addr16:bp) b byte (A) (io:bp) b
LH AH I S T N Z V C RMW
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Z Z Z - - - - - - - - - - - - - - - - - -
* * * - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - -
* * * * * * - - - - - - - - - - - - - - -
* * * * * * - - - - - - * * * * * * * - -
- - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - -
- - - * * * * * * * * * - - - - - - * - -
2x (b) bit (dir:bp) b (A) 2x (b) bit (addr16:bp) b (A) 2x (b) bit (io:bp) b (A) 2x (b) bit (dir:bp) b 1 2x (b) bit (addr16:bp) b 1 2x (b) bit (io:bp) b 1 2x (b) bit (dir:bp) b 0 2x (b) bit (addr16:bp) b 0 2x (b) bit (io:bp) b 0 (b) (b) (b) (b) (b) (b) 2x (b) *5 *5 Branch when (dir:bp) b = 0 Branch when (addr16:bp) b = 0 Branch when (io:bp) b = 0 Branch when (dir:bp) b = 1 Branch when (addr16:bp) b = 1 Branch when (io:bp) b = 1
Branch when (addr16:bp) b = 1, bit = 1
SBBS addr16:bp, rel WBTS io:bp WBTC io:bp *1: *2: *3: *4: *5:
Wait until (io:bp) b = 1 Wait until (io:bp) b = 0
8 when branching, 7 when not branching 7 when branching, 6 when not branching 10 when condition is satisfied, 9 when not satisfied Undefined count Until condition is satisfied
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." Table 23 Mnemonic SWAP SWAPW EXT EXTW ZEXT ZEXTW Accumulator Manipulation Instructions (Byte/Word) [6 Instructions] # 1 1 1 1 1 1 ~ 3 2 1 2 1 1
RG
B 0 0 0 0 0 0
Operation byte (A) 0 to 7 (A) 8 to 15 word (AH) (AL) byte sign extension word sign extension byte zero extension word zero extension
LH
AH
I
S
T
N
Z
V
C
RMW
0 0 0 0 0 0
- - X - Z -
- * - X - Z
- - - - - -
- - - - - -
- - - - - -
- - * * R R
- - * * * *
- - - - - -
- - - - - -
- - - - - -
70
MB90550A Series
Table 24 Mnemonic MOVS/MOVSI MOVSD SCEQ/SCEQI SCEQD FISL/FILSI # 2 2 2 2 ~ * *2 *1 *1
2
String Instructions [10 Instructions] Operation
LH AH I S T N Z V C RMW
RG
B * *3 *4 *4 *3 *6 *6 *7 *7 *6
3
* *5 *5 *5
5
Byte transfer @AH+ @AL+, counter = RW0 Byte transfer @AH- @AL-, counter = RW0 Byte retrieval (@AH+) - AL, counter = RW0 Byte retrieval (@AH-) - AL, counter = RW0 Byte filling @AH+ AL, counter = RW0 Word transfer @AH+ @AL+, counter = RW0 Word transfer @AH- @AL-, counter = RW0 Word retrieval (@AH+) - AL, counter = RW0 Word retrieval (@AH-) - AL, counter = RW0 Word filling @AH+ AL, counter = RW0
- - - - - - - - - -
- - - - - - - - - -
- - - - - - - - - -
- - - - - - - - - -
- - - - - - - - - -
- - * * * - - * * *
- - * * * - - * * *
- - * * - - - * * -
- - * * - - - * * -
- - - - - - - - - -
2 6m +6 *5 *2 *2 *1 *1 *8 *8 *8 *8
MOVSW/MOVSWI 2 MOVSWD 2 SCWEQ/SCWEQI SCWEQD FILSW/FILSWI 2 2
2 6m +6 *8
m: RW0 value (counter value) n: Loop count *1: 5 when RW0 is 0, 4 + 7 x (RW0) for count out, and 7 x n + 5 when match occurs *2: 5 when RW0 is 0, 4 + 8 x (RW0) in any other case *3: (b) x (RW0) + (b) x (RW0) when accessing different areas for the source and destination, calculate (b) separately for each. *4: (b) x n *5: 2 x (RW0) *6: (c) x (RW0) + (c) x (RW0) when accessing different areas for the source and destination, calculate (c) separately for each. *7: (c) x n *8: 2 x (RW0) Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
71
MB90550A Series
s ORDERING INFORMATION
Part number MB90552APF MB90553APF MB90T552APF MB90T553APF MB90F553APF MB90P553APF MB90552APF MB90553APF MB90T552APF MB90T553APF MB90F553APF MB90P553APF Package Remarks
100-pin plastic QFP (FPT-100P-M06)
100-pin plastic LQFP (FPT-100P-M05)
72
MB90550A Series
s PACKAGE DIMENSIONS
100-pin plastic QFP (FPT-100P-M06)
23.900.40(.941.016) 20.000.20(.787.008)
80 81 51 50
3.35(.132)MAX (Mounting height) 0.05(.002)MIN (STAND OFF)
14.000.20 (.551.008)
INDEX
100 31
17.900.40 (.705.016)
12.35(.486) REF
16.300.40 (.642.016)
"A" LEAD No.
1 30
0.65(.0256)TYP
0.300.10 (.012.004)
0.13(.005)
M
0.150.05(.006.002)
Details of "A" part 0.25(.010) "B" 0.10(.004) 18.85(.742)REF 22.300.40(.878.016) 0.30(.012) 0.18(.007)MAX 0.53(.021)MAX Details of "B" part
0
10
0.800.20 (.031.008)
C
1994 FUJITSU LIMITED F100008-3C-2
Dimensions in mm (inches) 100-pin plastic LQFP (FPT-100P-M05)
16.000.20(.630.008)SQ
75
1.50 -0.10
51
+0.20 +.008
(Mouting height)
14.000.10(.551.004)SQ
.059 -.004
76
50
12.00 (.472) REF INDEX
15.00 (.591) NOM
Details of "A" part 0.15(.006)
100
26
0.15(.006) 0.15(.006)MAX
LEAD No.
1
25
"B"
+0.05 -0.02 +.002 -.001
"A" 0.50(.0197)TYP 0.18 .007
+0.08 -0.03 +.003 -.001
0.40(.016)MAX 0.127 .005
0.08(.003)
M
Details of "B" part 0.100.10 (STAND OFF) (.004.004)
0.10(.004)
0.500.20(.020.008) 0~10
C
1995 FUJITSU LIMITED F100007S-2C-3
Dimensions in mm (inches) 73
MB90550A Series
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: 81(44) 754-3763 Fax: 81(44) 754-3329
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
http://www.fujitsu.co.jp/
North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
http://www.fmap.com.sg/
F9910 (c) FUJITSU LIMITED Printed in Japan

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